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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-07 15:30:21 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-01-08 14:27:43 +0000 |
| commit | d25109905aa46fce557d2905a43c347ca5be1aa0 (patch) | |
| tree | d4eca1b950e3f394a3b58a6a02bcd26a25b1be18 /src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | |
| parent | 458297c8ba237808a3cdf698f9c7c561b13c0b6c (diff) | |
| download | coreboot-d25109905aa46fce557d2905a43c347ca5be1aa0.tar.xz | |
mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetree
The devicetree was synced incorrectly with respect to the function
disable register set in romstage.
Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30711
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 9f92d2adf5..05edb278d9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/x4x # Northbridge subsystemid 0x1458 0xe000 end end - device pci 1c.2 on end # PCIe 3 + device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 device pci 1c.4 off end # PCIe 5 device pci 1c.5 off end # PCIe 6 |