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author | Damien Zammit <damien@zamaudio.com> | 2015-08-19 15:23:32 +1000 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2015-12-30 22:21:01 +0100 |
commit | cbe7a8e1008009c45551b56171da5df79a07fcce (patch) | |
tree | 759624ca71e905c443e4078e8b84c98711d7d93a /src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | |
parent | 4b513a618d7d7edeb5ed9c5073e838b46e2f4676 (diff) | |
download | coreboot-cbe7a8e1008009c45551b56171da5df79a07fcce.tar.xz |
gigabyte/ga-g41m-es2l: Add mainboard
Board uses x4x native raminit
Board boots into Debian 8 with full graphics
IRQ9: nobody cared, gets disabled
(PIC needs IRQ settings?)
VGA:
- VGA native init works in grub with analog connector
- Fails to boot with both channels of ram populated
Change-Id: I7417813456817529b8cbaace45cefe47467d0a82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl')
-rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl new file mode 100644 index 0000000000..e11eb39542 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} |