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authorNico Huber <nico.h@gmx.de>2019-07-20 17:03:56 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-07-20 15:27:01 +0000
commitae317695e3f03d55fbba1805ff06e004383e67c8 (patch)
tree043aa5f7b46a16df85322a3c38071b0eaa428422 /src/mainboard/gigabyte/ga-g41m-es2l
parent0db6e7569da8aff8d868afd65027c075b4710fa4 (diff)
downloadcoreboot-ae317695e3f03d55fbba1805ff06e004383e67c8.tar.xz
mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx: Detect if the southbridge supports AHCI) but we forgot to update the `chip.h` and devicetrees. Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-g41m-es2l')
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index d24eb5d6ac..7045dbf8e1 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -45,7 +45,6 @@ chip northbridge/intel/x4x # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
- register "ide_legacy_combined" = "0x0" # Combined mode broken
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ports_implemented" = "0x3"