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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-19 10:56:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-30 08:54:30 +0000 |
| commit | 0c0b16ac9e8ae62533f3029aa1a9f33506222dce (patch) | |
| tree | 3f0f5a2bd4ef53dd6d6ebd753d48c9d1567280a6 /src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb | |
| parent | 95cdd9f21bdf4191f5b0f4c617fb398462d8a647 (diff) | |
| download | coreboot-0c0b16ac9e8ae62533f3029aa1a9f33506222dce.tar.xz | |
mb/gigabyte/ga-h61m-*: Use overridetrees
Make use of overridetrees, as these mainboards are very similar.
Tested on GA-H61MA-D3V, still works fine.
Change-Id: I1b587a091da631cb172eb76722958da6c7518893
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39668
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb')
| -rw-r--r-- | src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb new file mode 100644 index 0000000000..14778097e6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb @@ -0,0 +1,46 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1458 0x5000 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end |