mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant

Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.

The GA-H61M-S2PV has been boot-tested too, it still boots.

Working:
 - S3 suspend/resume
 - USB ports and headers (Intel USB2 and EtronTech USB3)
 - Gigabit Ethernet
 - Integrated DVI/VGA graphics (libgfxinit)
 - PCIe x16 graphics
 - PCIe x1 ports
 - PS/2 port with a keyboard
 - SATA controllers (Intel SATA2 and Marvell SATA3)
 - User-space fan control (fancontrol on Linux)
 - Native raminit (4+4GB DDR3-1333)
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware. Backup chip is untested.

Untested:
 - VGA BIOS for integrated graphics init
 - Audio: Only front/read outputs has been tested.
 - Non-Linux OSes
 - ACPI thermal zone and OS-independent fan control

Not working:
 - Default IFD defines the BIOS region as the entire flash chip.
   Using 'flashrom --ifd -i bios' is asking for a failed flash!

Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 101 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb
new file mode 100644
index 0000000000..22d483e12a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb
@@ -0,0 +1,101 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+	register "gfx.ndid" = "3"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/model_206ax
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0x0 on	end
+			device lapic 0xacac off	end
+		end
+	end
+	register "pci_mmio_size" = "2048"
+	device domain 0x0 on
+		subsystemid 0x1458 0x5001 inherit
+		device pci 00.0 on end	# Host bridge
+		device pci 01.0 on end	# PCIe Bridge for discrete graphics
+		device pci 02.0 on end	# Internal graphics
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "c2_latency" = "0x0065"
+			register "gen1_dec" = "0x003c0a01"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x33"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			device pci 16.0 on  end	# Management Engine Interface 1
+			device pci 16.1 off end	# Management Engine Interface 2
+			device pci 1a.0 on  end	# USB2 EHCI #2
+			device pci 1b.0 on  end	# High Definition Audio Audio controller
+			device pci 1c.0 on  end	# PCIe Port #1
+			device pci 1c.1 on  end	# PCIe Port #2
+			device pci 1c.2 on  end	# PCIe Port #3
+			device pci 1c.3 on  end	# PCIe Port #4
+			device pci 1c.4 on  end	# PCIe Port #5
+			device pci 1c.5 on  end	# PCIe Port #6
+			device pci 1d.0 on  end	# USB2 EHCI #1
+			device pci 1e.0 off end	# PCI bridge
+			device pci 1f.0 on	# LPC bridge
+				chip superio/ite/it8728f
+					device pnp 2e.0 off end	# Floppy
+					device pnp 2e.1 off end	# COM1
+					device pnp 2e.2 off end	# COM2
+					device pnp 2e.3 off end	# Parallel port
+					device pnp 2e.4 on	# Environment Controller
+						io 0x60 = 0x0a30
+						io 0x62 = 0x0a20
+						irq 0x70 = 9
+						irq 0xf2 = 0x40
+					end
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0xf0 = 0x08
+					end
+					device pnp 2e.6 on	# Mouse
+						irq 0x70 = 12
+					end
+					device pnp 2e.7 on	# GPIO
+						irq 0x25 = 0x40
+						irq 0x26 = 0xf7
+						irq 0x27 = 0x10
+						irq 0x2c = 0x80
+						io 0x60 = 0x0000
+						io 0x62 = 0x0a00
+						io 0x64 = 0x0000
+						irq 0x73 = 0x00
+						irq 0xcb = 0x00
+						irq 0xf0 = 0x10
+						irq 0xf1 = 0x40
+						irq 0xf6 = 0x1c
+					end
+					device pnp 2e.a off end	 # CIR
+				end
+			end
+			device pci 1f.2 on  end	# SATA Controller 1
+			device pci 1f.3 on  end	# SMBus
+			device pci 1f.5 off end	# SATA Controller 2
+			device pci 1f.6 on  end	# Thermal
+		end
+	end
+end