mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-series

It is not a single mainboard anymore, it's actually three variants.

Change-Id: I66f1239abadd8bf93269d6d4617329dc4b925e8d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

28 files changed, 0 insertions, 1434 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
deleted file mode 100644
index 67cefd1c0f..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_4096
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select INTEL_INT15
-	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-	select SERIRQ_CONTINUOUS_MODE
-	select SOUTHBRIDGE_INTEL_BD82X6X
-	select USE_NATIVE_RAMINIT
-	select SUPERIO_ITE_IT8728F
-	select MAINBOARD_HAS_LIBGFXINIT
-	select INTEL_GMA_HAVE_VBT
-	select HAVE_OPTION_TABLE
-	select HAVE_CMOS_DEFAULT
-
-config MAINBOARD_DIR
-	string
-	default "gigabyte/ga-h61m-s2pv"
-
-config VARIANT_DIR
-	string
-	default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV
-	default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V
-	default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV
-	default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V
-	default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
-
-config OVERRIDE_DEVICETREE
-	string
-	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
-config MAX_CPUS
-	int
-	default 8
-
-# Override the default variant behavior, since the data.vbt is the same
-config INTEL_GMA_VBT_FILE
-	default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
-
-config USBDEBUG_HCD_INDEX # Bottom left port seen from rear
-	int
-	default 2
-
-endif # BOARD_GIGABYTE_GA_H61M*
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
deleted file mode 100644
index 15d107d8e5..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name
+++ /dev/null
@@ -1,10 +0,0 @@
-config BOARD_GIGABYTE_GA_H61M_S2PV
-	bool "GA-H61M-S2PV"
-
-config BOARD_GIGABYTE_GA_H61M_DS2V
-	bool "GA-H61M-DS2V"
-	select NO_UART_ON_SUPERIO
-
-config BOARD_GIGABYTE_GA_H61MA_D3V
-	bool "GA-H61MA-D3V"
-	select NO_UART_ON_SUPERIO
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
deleted file mode 100644
index 9916927d25..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc
+++ /dev/null
@@ -1,7 +0,0 @@
-bootblock-y += variants/$(VARIANT_DIR)/gpio.c
-romstage-y += variants/$(VARIANT_DIR)/gpio.c
-
-ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-bootblock-y += early_init.c
-romstage-y += early_init.c
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl
deleted file mode 100644
index 0483c161be..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/mainboard.asl
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope (\_SB)
-{
-	Device (PWRB)
-	{
-		Name (_HID, EisaId("PNP0C0C"))
-	}
-}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl
deleted file mode 100644
index 92c98614d7..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/platform.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl
deleted file mode 100644
index 606085fafe..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/superio.asl
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl
deleted file mode 100644
index c035abbcce..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Thermal Zone
-
-External (\PPKG, MethodObj)
-
-Scope (\_TZ)
-{
-	ThermalZone (THRM)
-	{
-		Name (_TC1, 0x02)
-		Name (_TC2, 0x03)
-
-		// Thermal zone polling frequency: 10 seconds
-		Name (_TZP, 100)
-
-		// Thermal sampling period for passive cooling: 10 seconds
-		Name (_TSP, 100)
-
-		// Convert from Degrees C to 1/10 Kelvin for ACPI
-		Method (CTOK, 1)
-		{
-			// 10th of Degrees C
-			Multiply (Arg0, 10, Local0)
-
-			// Convert to Kelvin
-			Add (Local0, 2732, Local0)
-
-			Return (Local0)
-		}
-
-		// Threshold for OS to shutdown
-		Method (_CRT, 0, Serialized)
-		{
-			Return (CTOK (\TCRT))
-		}
-
-		// Threshold for passive cooling
-		Method (_PSV, 0, Serialized)
-		{
-			Return (CTOK (\TPSV))
-		}
-
-		// Processors used for passive cooling
-		Method (_PSL, 0, Serialized)
-		{
-			Return (\PPKG ())
-		}
-	}
-}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c
deleted file mode 100644
index 5a6a5e4de4..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/acpi_tables.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/bd82x6x/nvs.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt b/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt
deleted file mode 100644
index ef0d22c07e..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: desktop
-Board URL: https://www.gigabyte.com/Motherboard/GA-H61M-S2PV-rev-23#ov
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default
deleted file mode 100644
index 6f3cec735e..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.default
+++ /dev/null
@@ -1,6 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-power_on_after_fail=Enable
-nmi=Enable
-sata_mode=AHCI
-gfx_uma_size=32M
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout b/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout
deleted file mode 100644
index c31d568140..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/cmos.layout
+++ /dev/null
@@ -1,105 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-
-#411       10       r       0        unused
-421         1       e       9        sata_mode
-#422        2       r       0        unused
-
-# coreboot config options: cpu
-#425        7       r       0        unused
-
-# coreboot config options: northbridge
-432         3        e      11        gfx_uma_size
-#435        549       r       0        unused
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-9     0     AHCI
-9     1     IDE
-11    0     32M
-11    1     64M
-11    2     96M
-11    3     128M
-11    4     160M
-11    5     192M
-11    6     224M
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 439 984
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt b/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt
deleted file mode 100644
index 3d230d99de..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/data.vbt
+++ /dev/null
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
deleted file mode 100644
index 14778097e6..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
+++ /dev/null
@@ -1,46 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-## This file is part of the coreboot project.
-
-chip northbridge/intel/sandybridge
-	device cpu_cluster 0 on
-		chip cpu/intel/model_206ax
-			register "c1_acpower" = "1"
-			register "c1_battery" = "1"
-			register "c2_acpower" = "3"
-			register "c2_battery" = "3"
-			register "c3_acpower" = "5"
-			register "c3_battery" = "5"
-			device lapic 0 on	end
-			device lapic 0xacac off	end
-		end
-	end
-	register "pci_mmio_size" = "2048"
-	device domain 0 on
-		subsystemid 0x1458 0x5000 inherit
-
-		device pci 00.0 on end	# Host bridge
-		device pci 01.0 on end	# PEG
-		device pci 02.0 on end	# iGPU
-
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "c2_latency" = "0x0065"
-			register "gen1_dec" = "0x003c0a01"
-			register "sata_interface_speed_support" = "0x3"
-			register "sata_port_map" = "0x33"
-			register "spi_lvscc" = "0x2005"
-			register "spi_uvscc" = "0x2005"
-
-			device pci 16.0 on  end	# MEI #1
-			device pci 1a.0 on  end	# USB2 EHCI #2
-			device pci 1b.0 on  end	# HD Audio
-
-			device pci 1d.0 on  end	# USB2 EHCI #1
-			device pci 1e.0 off end	# PCI bridge
-			device pci 1f.0 on  end	# LPC bridge
-			device pci 1f.2 on  end	# SATA Controller 1
-			device pci 1f.3 on  end	# SMBus
-			device pci 1f.5 off end	# SATA Controller 2
-			device pci 1f.6 on  end	# Thermal
-		end
-	end
-end
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
deleted file mode 100644
index 61eb8efeb9..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-
-#include <arch/acpi.h>
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20141018	// OEM revision
-)
-{
-	#include "acpi/mainboard.asl"
-	#include "acpi/platform.asl"
-	#include "acpi/superio.asl"
-	#include "acpi/thermal.asl"
-	#include <cpu/intel/common/acpi/cpu.asl>
-	#include <southbridge/intel/common/acpi/platform.asl>
-
-	/* global NVS and variables. */
-	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	Device (\_SB.PCI0)
-	{
-		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-	}
-}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c
deleted file mode 100644
index d006745f1b..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8728f/it8728f.h>
-
-#define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO)
-#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	{ 1, 0, 0 },
-	{ 1, 0, 0 },
-	{ 1, 0, 1 },
-	{ 1, 0, 1 },
-	{ 1, 0, 2 },
-	{ 1, 0, 2 },
-	{ 1, 0, 3 },
-	{ 1, 0, 3 },
-	{ 1, 0, 4 },
-	{ 1, 0, 4 },
-	{ 1, 0, 6 },
-	{ 1, 0, 5 },
-	{ 1, 0, 5 },
-	{ 1, 0, 6 },
-};
-
-void bootblock_mainboard_early_init(void)
-{
-	if (!CONFIG(NO_UART_ON_SUPERIO)) {
-		/* Enable serial port */
-		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	}
-
-	/* Disable SIO WDT which kicks in DualBIOS */
-	ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads
deleted file mode 100644
index daa6c0f877..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/gma-mainboard.ads
+++ /dev/null
@@ -1,17 +0,0 @@
--- SPDX-License-Identifier: GPL-2.0-only
--- This file is part of the coreboot project.
-
-with HW.GFX.GMA;
-with HW.GFX.GMA.Display_Probing;
-
-use HW.GFX.GMA;
-use HW.GFX.GMA.Display_Probing;
-
-private package GMA.Mainboard is
-
-   ports : constant Port_List :=
-     (HDMI1,
-      Analog,
-      others => Disabled);
-
-end GMA.Mainboard;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
+++ /dev/null
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c b/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c
deleted file mode 100644
index e14e31c041..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/mainboard.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <drivers/intel/gma/int15.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-static void mainboard_enable(struct device *dev)
-{
-	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
-					GMA_INT15_PANEL_FIT_DEFAULT,
-					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c
deleted file mode 100644
index a438cda4fa..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/gpio.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/common/gpio.h>
-
-static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-	.gpio0 = GPIO_MODE_GPIO,
-	.gpio1 = GPIO_MODE_GPIO,
-	.gpio2 = GPIO_MODE_GPIO,
-	.gpio3 = GPIO_MODE_GPIO,
-	.gpio4 = GPIO_MODE_GPIO,
-	.gpio5 = GPIO_MODE_GPIO,
-	.gpio6 = GPIO_MODE_GPIO,
-	.gpio7 = GPIO_MODE_GPIO,
-	.gpio8 = GPIO_MODE_GPIO,
-	.gpio9 = GPIO_MODE_NATIVE,
-	.gpio10 = GPIO_MODE_NATIVE,
-	.gpio11 = GPIO_MODE_NATIVE,
-	.gpio12 = GPIO_MODE_GPIO,
-	.gpio13 = GPIO_MODE_GPIO,
-	.gpio14 = GPIO_MODE_NATIVE,
-	.gpio15 = GPIO_MODE_GPIO,
-	.gpio16 = GPIO_MODE_GPIO,
-	.gpio17 = GPIO_MODE_GPIO,
-	.gpio18 = GPIO_MODE_NATIVE,
-	.gpio19 = GPIO_MODE_GPIO,
-	.gpio20 = GPIO_MODE_NATIVE,
-	.gpio21 = GPIO_MODE_GPIO,
-	.gpio22 = GPIO_MODE_GPIO,
-	.gpio23 = GPIO_MODE_NATIVE,
-	.gpio24 = GPIO_MODE_GPIO,
-	.gpio25 = GPIO_MODE_NATIVE,
-	.gpio26 = GPIO_MODE_NATIVE,
-	.gpio27 = GPIO_MODE_GPIO,
-	.gpio28 = GPIO_MODE_GPIO,
-	.gpio29 = GPIO_MODE_GPIO,
-	.gpio30 = GPIO_MODE_NATIVE,
-	.gpio31 = GPIO_MODE_GPIO,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-	.gpio0 = GPIO_DIR_INPUT,
-	.gpio1 = GPIO_DIR_INPUT,
-	.gpio2 = GPIO_DIR_INPUT,
-	.gpio3 = GPIO_DIR_INPUT,
-	.gpio4 = GPIO_DIR_INPUT,
-	.gpio5 = GPIO_DIR_INPUT,
-	.gpio6 = GPIO_DIR_INPUT,
-	.gpio7 = GPIO_DIR_INPUT,
-	.gpio8 = GPIO_DIR_OUTPUT,
-	.gpio12 = GPIO_DIR_OUTPUT,
-	.gpio13 = GPIO_DIR_INPUT,
-	.gpio15 = GPIO_DIR_OUTPUT,
-	.gpio16 = GPIO_DIR_INPUT,
-	.gpio17 = GPIO_DIR_INPUT,
-	.gpio19 = GPIO_DIR_INPUT,
-	.gpio21 = GPIO_DIR_INPUT,
-	.gpio22 = GPIO_DIR_INPUT,
-	.gpio24 = GPIO_DIR_OUTPUT,
-	.gpio27 = GPIO_DIR_INPUT,
-	.gpio28 = GPIO_DIR_OUTPUT,
-	.gpio29 = GPIO_DIR_INPUT,
-	.gpio31 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_level = {
-	.gpio8 = GPIO_LEVEL_HIGH,
-	.gpio12 = GPIO_LEVEL_HIGH,
-	.gpio15 = GPIO_LEVEL_LOW,
-	.gpio24 = GPIO_LEVEL_LOW,
-	.gpio28 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-	.gpio24 = GPIO_RESET_RSMRST,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-	.gpio13 = GPIO_INVERT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-	.gpio32 = GPIO_MODE_GPIO,
-	.gpio33 = GPIO_MODE_GPIO,
-	.gpio34 = GPIO_MODE_GPIO,
-	.gpio35 = GPIO_MODE_GPIO,
-	.gpio36 = GPIO_MODE_GPIO,
-	.gpio37 = GPIO_MODE_GPIO,
-	.gpio38 = GPIO_MODE_GPIO,
-	.gpio39 = GPIO_MODE_GPIO,
-	.gpio40 = GPIO_MODE_NATIVE,
-	.gpio41 = GPIO_MODE_NATIVE,
-	.gpio42 = GPIO_MODE_NATIVE,
-	.gpio43 = GPIO_MODE_NATIVE,
-	.gpio44 = GPIO_MODE_NATIVE,
-	.gpio45 = GPIO_MODE_NATIVE,
-	.gpio46 = GPIO_MODE_NATIVE,
-	.gpio47 = GPIO_MODE_NATIVE,
-	.gpio48 = GPIO_MODE_GPIO,
-	.gpio49 = GPIO_MODE_GPIO,
-	.gpio50 = GPIO_MODE_NATIVE,
-	.gpio51 = GPIO_MODE_NATIVE,
-	.gpio52 = GPIO_MODE_NATIVE,
-	.gpio53 = GPIO_MODE_NATIVE,
-	.gpio54 = GPIO_MODE_NATIVE,
-	.gpio55 = GPIO_MODE_NATIVE,
-	.gpio56 = GPIO_MODE_NATIVE,
-	.gpio57 = GPIO_MODE_GPIO,
-	.gpio58 = GPIO_MODE_NATIVE,
-	.gpio59 = GPIO_MODE_NATIVE,
-	.gpio60 = GPIO_MODE_NATIVE,
-	.gpio61 = GPIO_MODE_NATIVE,
-	.gpio62 = GPIO_MODE_NATIVE,
-	.gpio63 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-	.gpio32 = GPIO_DIR_OUTPUT,
-	.gpio33 = GPIO_DIR_OUTPUT,
-	.gpio34 = GPIO_DIR_INPUT,
-	.gpio35 = GPIO_DIR_OUTPUT,
-	.gpio36 = GPIO_DIR_INPUT,
-	.gpio37 = GPIO_DIR_INPUT,
-	.gpio38 = GPIO_DIR_INPUT,
-	.gpio39 = GPIO_DIR_INPUT,
-	.gpio48 = GPIO_DIR_INPUT,
-	.gpio49 = GPIO_DIR_INPUT,
-	.gpio57 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_level = {
-	.gpio32 = GPIO_LEVEL_HIGH,
-	.gpio33 = GPIO_LEVEL_HIGH,
-	.gpio35 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-	.gpio64 = GPIO_MODE_NATIVE,
-	.gpio65 = GPIO_MODE_NATIVE,
-	.gpio66 = GPIO_MODE_NATIVE,
-	.gpio67 = GPIO_MODE_NATIVE,
-	.gpio68 = GPIO_MODE_GPIO,
-	.gpio69 = GPIO_MODE_GPIO,
-	.gpio70 = GPIO_MODE_NATIVE,
-	.gpio71 = GPIO_MODE_NATIVE,
-	.gpio72 = GPIO_MODE_GPIO,
-	.gpio73 = GPIO_MODE_NATIVE,
-	.gpio74 = GPIO_MODE_NATIVE,
-	.gpio75 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-	.gpio68 = GPIO_DIR_INPUT,
-	.gpio69 = GPIO_DIR_INPUT,
-	.gpio72 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_level = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-};
-
-const struct pch_gpio_map mainboard_gpio_map = {
-	.set1 = {
-		.mode		= &pch_gpio_set1_mode,
-		.direction	= &pch_gpio_set1_direction,
-		.level		= &pch_gpio_set1_level,
-		.blink		= &pch_gpio_set1_blink,
-		.invert		= &pch_gpio_set1_invert,
-		.reset		= &pch_gpio_set1_reset,
-	},
-	.set2 = {
-		.mode		= &pch_gpio_set2_mode,
-		.direction	= &pch_gpio_set2_direction,
-		.level		= &pch_gpio_set2_level,
-		.reset		= &pch_gpio_set2_reset,
-	},
-	.set3 = {
-		.mode		= &pch_gpio_set3_mode,
-		.direction	= &pch_gpio_set3_direction,
-		.level		= &pch_gpio_set3_level,
-		.reset		= &pch_gpio_set3_reset,
-	},
-};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c
deleted file mode 100644
index 069ba8fade..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/hda_verb.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Realtek ALC887 */
-	0x1458a002,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
-	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x16, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x17, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb
deleted file mode 100644
index 4e3b21bfe2..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-ds2v/overridetree.cb
+++ /dev/null
@@ -1,52 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-## This file is part of the coreboot project.
-
-chip northbridge/intel/sandybridge
-	device domain 0 on
-
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-
-			device pci 1c.0 on  end	# RP #1: PCIe x1 Port (PCIEX1_3)
-			device pci 1c.1 on  end	# RP #2: PCIe x1 Port (PCIEX1_1)
-			device pci 1c.2 off end	# RP #3:
-			device pci 1c.3 off end	# RP #4:
-			device pci 1c.4 on  end	# RP #5: Realtek RTL8111F GbE NIC
-			device pci 1c.5 on  end	# RP #6: PCIe x1 Port (PCIEX1_2)
-
-			device pci 1f.0 on	# LPC bridge
-				chip superio/ite/it8728f
-					device pnp 2e.0 off end	# Floppy
-					device pnp 2e.1 off end	# COM1
-					device pnp 2e.2 off end	# COM2
-					device pnp 2e.3 off end	# Parallel port
-					device pnp 2e.4 on	# Environment Controller
-						io 0x60 = 0x0a30
-						io 0x62 = 0x0a20
-					end
-					device pnp 2e.5 on	# Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-					end
-					device pnp 2e.6 on  end	# Mouse
-					device pnp 2e.7 on	# GPIO
-						irq 0x25 = 0x40
-						irq 0x26 = 0xf7
-						irq 0x27 = 0x10
-						irq 0x2c = 0x80
-						io 0x60  = 0x0000
-						io 0x62  = 0x0a00
-						io 0x64  = 0x0000
-						irq 0x70 = 0x00
-						irq 0x73 = 0x00
-						irq 0xc1 = 0x37
-						irq 0xcb = 0x00
-						irq 0xf0 = 0x10
-						irq 0xf1 = 0x42
-						irq 0xf6 = 0x1c
-					end
-					device pnp 2e.a off end	# CIR
-				end
-			end
-		end
-	end
-end
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c
deleted file mode 100644
index 800298d882..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/common/gpio.h>
-
-static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-	.gpio0 = GPIO_MODE_GPIO,
-	.gpio1 = GPIO_MODE_GPIO,
-	.gpio2 = GPIO_MODE_GPIO,
-	.gpio3 = GPIO_MODE_GPIO,
-	.gpio4 = GPIO_MODE_GPIO,
-	.gpio5 = GPIO_MODE_GPIO,
-	.gpio6 = GPIO_MODE_GPIO,
-	.gpio7 = GPIO_MODE_GPIO,
-	.gpio8 = GPIO_MODE_GPIO,
-	.gpio9 = GPIO_MODE_NATIVE,
-	.gpio10 = GPIO_MODE_NATIVE,
-	.gpio11 = GPIO_MODE_NATIVE,
-	.gpio12 = GPIO_MODE_GPIO,
-	.gpio13 = GPIO_MODE_GPIO,
-	.gpio14 = GPIO_MODE_NATIVE,
-	.gpio15 = GPIO_MODE_GPIO,
-	.gpio16 = GPIO_MODE_GPIO,
-	.gpio17 = GPIO_MODE_GPIO,
-	.gpio18 = GPIO_MODE_NATIVE,
-	.gpio19 = GPIO_MODE_GPIO,
-	.gpio20 = GPIO_MODE_NATIVE,
-	.gpio21 = GPIO_MODE_GPIO,
-	.gpio22 = GPIO_MODE_GPIO,
-	.gpio23 = GPIO_MODE_NATIVE,
-	.gpio24 = GPIO_MODE_GPIO,
-	.gpio25 = GPIO_MODE_NATIVE,
-	.gpio26 = GPIO_MODE_NATIVE,
-	.gpio27 = GPIO_MODE_GPIO,
-	.gpio28 = GPIO_MODE_GPIO,
-	.gpio29 = GPIO_MODE_GPIO,
-	.gpio30 = GPIO_MODE_NATIVE,
-	.gpio31 = GPIO_MODE_GPIO,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-	.gpio0 = GPIO_DIR_INPUT,
-	.gpio1 = GPIO_DIR_INPUT,
-	.gpio2 = GPIO_DIR_INPUT,
-	.gpio3 = GPIO_DIR_INPUT,
-	.gpio4 = GPIO_DIR_INPUT,
-	.gpio5 = GPIO_DIR_INPUT,
-	.gpio6 = GPIO_DIR_INPUT,
-	.gpio7 = GPIO_DIR_INPUT,
-	.gpio8 = GPIO_DIR_OUTPUT,
-	.gpio12 = GPIO_DIR_OUTPUT,
-	.gpio13 = GPIO_DIR_INPUT,
-	.gpio15 = GPIO_DIR_OUTPUT,
-	.gpio16 = GPIO_DIR_INPUT,
-	.gpio17 = GPIO_DIR_INPUT,
-	.gpio19 = GPIO_DIR_INPUT,
-	.gpio21 = GPIO_DIR_INPUT,
-	.gpio22 = GPIO_DIR_INPUT,
-	.gpio24 = GPIO_DIR_OUTPUT,
-	.gpio27 = GPIO_DIR_INPUT,
-	.gpio28 = GPIO_DIR_OUTPUT,
-	.gpio29 = GPIO_DIR_INPUT,
-	.gpio31 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_level = {
-	.gpio8 = GPIO_LEVEL_HIGH,
-	.gpio12 = GPIO_LEVEL_HIGH,
-	.gpio15 = GPIO_LEVEL_LOW,
-	.gpio24 = GPIO_LEVEL_LOW,
-	.gpio28 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-	.gpio13 = GPIO_INVERT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-	.gpio32 = GPIO_MODE_GPIO,
-	.gpio33 = GPIO_MODE_GPIO,
-	.gpio34 = GPIO_MODE_GPIO,
-	.gpio35 = GPIO_MODE_GPIO,
-	.gpio36 = GPIO_MODE_GPIO,
-	.gpio37 = GPIO_MODE_GPIO,
-	.gpio38 = GPIO_MODE_GPIO,
-	.gpio39 = GPIO_MODE_GPIO,
-	.gpio40 = GPIO_MODE_NATIVE,
-	.gpio41 = GPIO_MODE_NATIVE,
-	.gpio42 = GPIO_MODE_NATIVE,
-	.gpio43 = GPIO_MODE_NATIVE,
-	.gpio44 = GPIO_MODE_NATIVE,
-	.gpio45 = GPIO_MODE_NATIVE,
-	.gpio46 = GPIO_MODE_NATIVE,
-	.gpio47 = GPIO_MODE_NATIVE,
-	.gpio48 = GPIO_MODE_GPIO,
-	.gpio49 = GPIO_MODE_GPIO,
-	.gpio50 = GPIO_MODE_NATIVE,
-	.gpio51 = GPIO_MODE_NATIVE,
-	.gpio52 = GPIO_MODE_NATIVE,
-	.gpio53 = GPIO_MODE_NATIVE,
-	.gpio54 = GPIO_MODE_NATIVE,
-	.gpio55 = GPIO_MODE_NATIVE,
-	.gpio56 = GPIO_MODE_NATIVE,
-	.gpio57 = GPIO_MODE_GPIO,
-	.gpio58 = GPIO_MODE_NATIVE,
-	.gpio59 = GPIO_MODE_NATIVE,
-	.gpio60 = GPIO_MODE_NATIVE,
-	.gpio61 = GPIO_MODE_NATIVE,
-	.gpio62 = GPIO_MODE_NATIVE,
-	.gpio63 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-	.gpio32 = GPIO_DIR_OUTPUT,
-	.gpio33 = GPIO_DIR_OUTPUT,
-	.gpio34 = GPIO_DIR_INPUT,
-	.gpio35 = GPIO_DIR_OUTPUT,
-	.gpio36 = GPIO_DIR_INPUT,
-	.gpio37 = GPIO_DIR_INPUT,
-	.gpio38 = GPIO_DIR_INPUT,
-	.gpio39 = GPIO_DIR_INPUT,
-	.gpio48 = GPIO_DIR_INPUT,
-	.gpio49 = GPIO_DIR_INPUT,
-	.gpio57 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_level = {
-	.gpio32 = GPIO_LEVEL_HIGH,
-	.gpio33 = GPIO_LEVEL_HIGH,
-	.gpio35 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-	.gpio64 = GPIO_MODE_NATIVE,
-	.gpio65 = GPIO_MODE_NATIVE,
-	.gpio66 = GPIO_MODE_NATIVE,
-	.gpio67 = GPIO_MODE_NATIVE,
-	.gpio68 = GPIO_MODE_GPIO,
-	.gpio69 = GPIO_MODE_GPIO,
-	.gpio70 = GPIO_MODE_NATIVE,
-	.gpio71 = GPIO_MODE_NATIVE,
-	.gpio72 = GPIO_MODE_GPIO,
-	.gpio73 = GPIO_MODE_NATIVE,
-	.gpio74 = GPIO_MODE_NATIVE,
-	.gpio75 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-	.gpio68 = GPIO_DIR_INPUT,
-	.gpio69 = GPIO_DIR_INPUT,
-	.gpio72 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_level = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-};
-
-const struct pch_gpio_map mainboard_gpio_map = {
-	.set1 = {
-		.mode		= &pch_gpio_set1_mode,
-		.direction	= &pch_gpio_set1_direction,
-		.level		= &pch_gpio_set1_level,
-		.blink		= &pch_gpio_set1_blink,
-		.invert		= &pch_gpio_set1_invert,
-		.reset		= &pch_gpio_set1_reset,
-	},
-	.set2 = {
-		.mode		= &pch_gpio_set2_mode,
-		.direction	= &pch_gpio_set2_direction,
-		.level		= &pch_gpio_set2_level,
-		.reset		= &pch_gpio_set2_reset,
-	},
-	.set3 = {
-		.mode		= &pch_gpio_set3_mode,
-		.direction	= &pch_gpio_set3_direction,
-		.level		= &pch_gpio_set3_level,
-		.reset		= &pch_gpio_set3_reset,
-	},
-};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c
deleted file mode 100644
index 069ba8fade..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Realtek ALC887 */
-	0x1458a002,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
-	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x16, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x17, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb
deleted file mode 100644
index 35f5144dec..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/overridetree.cb
+++ /dev/null
@@ -1,58 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-## This file is part of the coreboot project.
-
-chip northbridge/intel/sandybridge
-	device domain 0 on
-
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-
-			device pci 1c.0 on  end	# RP #1: PCIe x1 Port (PCIEX1)
-			device pci 1c.1 off end	# RP #2:
-			device pci 1c.2 off end	# RP #3:
-			device pci 1c.3 off end	# RP #4:
-			device pci 1c.4 on  end	# RP #5: Realtek RTL8111F GbE NIC
-			device pci 1c.5 on  end	# RP #6: ITE IT8892F PCIe to PCI bridge
-
-			device pci 1f.0 on	# LPC bridge
-				chip superio/ite/it8728f
-					device pnp 2e.0 off end		# Floppy
-					device pnp 2e.1 on		# COM1
-						io  0x60 = 0x03f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.2 off end		# COM2
-					device pnp 2e.3 on		# Parallel port
-						io  0x60 = 0x0378
-						irq 0x70 = 7
-						drq 0x74 = 4
-					end
-					device pnp 2e.4 on		# Environment Controller
-						io  0x60 = 0x0a30
-						irq 0x70 = 9
-						io  0x62 = 0x0a20
-					end
-					device pnp 2e.5 on		# Keyboard
-						io  0x60 = 0x60
-						irq 0x70 = 1
-						io  0x62 = 0x64
-					end
-					device pnp 2e.6 on		# Mouse
-						irq 0x70 = 12
-					end
-					device pnp 2e.7 on		# GPIO
-						irq 0x25 = 0x40
-						irq 0x27 = 0x10
-						irq 0x2c = 0x80
-						io  0x60 = 0x0000
-						io  0x62 = 0x0a00
-						io  0x64 = 0x0000
-						irq 0x70 = 0x00
-						irq 0xcb = 0x00
-						irq 0xf1 = 0x40
-					end
-					device pnp 2e.a off end		# CIR
-				end
-			end
-		end
-	end
-end
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c
deleted file mode 100644
index d24d16233d..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <southbridge/intel/common/gpio.h>
-
-static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-	.gpio0 = GPIO_MODE_GPIO,
-	.gpio1 = GPIO_MODE_GPIO,
-	.gpio2 = GPIO_MODE_GPIO,
-	.gpio3 = GPIO_MODE_GPIO,
-	.gpio4 = GPIO_MODE_GPIO,
-	.gpio5 = GPIO_MODE_GPIO,
-	.gpio6 = GPIO_MODE_GPIO,
-	.gpio7 = GPIO_MODE_GPIO,
-	.gpio8 = GPIO_MODE_GPIO,
-	.gpio9 = GPIO_MODE_NATIVE,
-	.gpio10 = GPIO_MODE_NATIVE,
-	.gpio11 = GPIO_MODE_NATIVE,
-	.gpio12 = GPIO_MODE_GPIO,
-	.gpio13 = GPIO_MODE_GPIO,
-	.gpio14 = GPIO_MODE_NATIVE,
-	.gpio15 = GPIO_MODE_GPIO,
-	.gpio16 = GPIO_MODE_GPIO,
-	.gpio17 = GPIO_MODE_GPIO,
-	.gpio18 = GPIO_MODE_NATIVE,
-	.gpio19 = GPIO_MODE_GPIO,
-	.gpio20 = GPIO_MODE_NATIVE,
-	.gpio21 = GPIO_MODE_GPIO,
-	.gpio22 = GPIO_MODE_GPIO,
-	.gpio23 = GPIO_MODE_NATIVE,
-	.gpio24 = GPIO_MODE_GPIO,
-	.gpio25 = GPIO_MODE_NATIVE,
-	.gpio26 = GPIO_MODE_NATIVE,
-	.gpio27 = GPIO_MODE_GPIO,
-	.gpio28 = GPIO_MODE_GPIO,
-	.gpio29 = GPIO_MODE_GPIO,
-	.gpio30 = GPIO_MODE_NATIVE,
-	.gpio31 = GPIO_MODE_GPIO,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-	.gpio0 = GPIO_DIR_INPUT,
-	.gpio1 = GPIO_DIR_INPUT,
-	.gpio2 = GPIO_DIR_INPUT,
-	.gpio3 = GPIO_DIR_INPUT,
-	.gpio4 = GPIO_DIR_INPUT,
-	.gpio5 = GPIO_DIR_INPUT,
-	.gpio6 = GPIO_DIR_INPUT,
-	.gpio7 = GPIO_DIR_INPUT,
-	.gpio8 = GPIO_DIR_OUTPUT,
-	.gpio12 = GPIO_DIR_OUTPUT,
-	.gpio13 = GPIO_DIR_INPUT,
-	.gpio15 = GPIO_DIR_OUTPUT,
-	.gpio16 = GPIO_DIR_INPUT,
-	.gpio17 = GPIO_DIR_INPUT,
-	.gpio19 = GPIO_DIR_INPUT,
-	.gpio21 = GPIO_DIR_INPUT,
-	.gpio22 = GPIO_DIR_INPUT,
-	.gpio24 = GPIO_DIR_OUTPUT,
-	.gpio27 = GPIO_DIR_INPUT,
-	.gpio28 = GPIO_DIR_OUTPUT,
-	.gpio29 = GPIO_DIR_INPUT,
-	.gpio31 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_level = {
-	.gpio8 = GPIO_LEVEL_HIGH,
-	.gpio12 = GPIO_LEVEL_HIGH,
-	.gpio15 = GPIO_LEVEL_LOW,
-	.gpio24 = GPIO_LEVEL_LOW,
-	.gpio28 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-	.gpio24 = GPIO_RESET_RSMRST,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-	.gpio13 = GPIO_INVERT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-	.gpio32 = GPIO_MODE_GPIO,
-	.gpio33 = GPIO_MODE_GPIO,
-	.gpio34 = GPIO_MODE_GPIO,
-	.gpio35 = GPIO_MODE_GPIO,
-	.gpio36 = GPIO_MODE_GPIO,
-	.gpio37 = GPIO_MODE_GPIO,
-	.gpio38 = GPIO_MODE_GPIO,
-	.gpio39 = GPIO_MODE_GPIO,
-	.gpio40 = GPIO_MODE_NATIVE,
-	.gpio41 = GPIO_MODE_NATIVE,
-	.gpio42 = GPIO_MODE_NATIVE,
-	.gpio43 = GPIO_MODE_NATIVE,
-	.gpio44 = GPIO_MODE_NATIVE,
-	.gpio45 = GPIO_MODE_NATIVE,
-	.gpio46 = GPIO_MODE_NATIVE,
-	.gpio47 = GPIO_MODE_NATIVE,
-	.gpio48 = GPIO_MODE_GPIO,
-	.gpio49 = GPIO_MODE_GPIO,
-	.gpio50 = GPIO_MODE_NATIVE,
-	.gpio51 = GPIO_MODE_NATIVE,
-	.gpio52 = GPIO_MODE_NATIVE,
-	.gpio53 = GPIO_MODE_NATIVE,
-	.gpio54 = GPIO_MODE_NATIVE,
-	.gpio55 = GPIO_MODE_NATIVE,
-	.gpio56 = GPIO_MODE_NATIVE,
-	.gpio57 = GPIO_MODE_GPIO,
-	.gpio58 = GPIO_MODE_NATIVE,
-	.gpio59 = GPIO_MODE_NATIVE,
-	.gpio60 = GPIO_MODE_NATIVE,
-	.gpio61 = GPIO_MODE_NATIVE,
-	.gpio62 = GPIO_MODE_NATIVE,
-	.gpio63 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-	.gpio32 = GPIO_DIR_OUTPUT,
-	.gpio33 = GPIO_DIR_OUTPUT,
-	.gpio34 = GPIO_DIR_INPUT,
-	.gpio35 = GPIO_DIR_OUTPUT,
-	.gpio36 = GPIO_DIR_INPUT,
-	.gpio37 = GPIO_DIR_INPUT,
-	.gpio38 = GPIO_DIR_INPUT,
-	.gpio39 = GPIO_DIR_INPUT,
-	.gpio48 = GPIO_DIR_INPUT,
-	.gpio49 = GPIO_DIR_INPUT,
-	.gpio57 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_level = {
-	.gpio32 = GPIO_LEVEL_HIGH,
-	.gpio33 = GPIO_LEVEL_HIGH,
-	.gpio35 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-	.gpio64 = GPIO_MODE_NATIVE,
-	.gpio65 = GPIO_MODE_NATIVE,
-	.gpio66 = GPIO_MODE_NATIVE,
-	.gpio67 = GPIO_MODE_NATIVE,
-	.gpio68 = GPIO_MODE_GPIO,
-	.gpio69 = GPIO_MODE_GPIO,
-	.gpio70 = GPIO_MODE_NATIVE,
-	.gpio71 = GPIO_MODE_NATIVE,
-	.gpio72 = GPIO_MODE_GPIO,
-	.gpio73 = GPIO_MODE_NATIVE,
-	.gpio74 = GPIO_MODE_NATIVE,
-	.gpio75 = GPIO_MODE_NATIVE,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-	.gpio68 = GPIO_DIR_INPUT,
-	.gpio69 = GPIO_DIR_INPUT,
-	.gpio72 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_level = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-};
-
-const struct pch_gpio_map mainboard_gpio_map = {
-	.set1 = {
-		.mode		= &pch_gpio_set1_mode,
-		.direction	= &pch_gpio_set1_direction,
-		.level		= &pch_gpio_set1_level,
-		.blink		= &pch_gpio_set1_blink,
-		.invert		= &pch_gpio_set1_invert,
-		.reset		= &pch_gpio_set1_reset,
-	},
-	.set2 = {
-		.mode		= &pch_gpio_set2_mode,
-		.direction	= &pch_gpio_set2_direction,
-		.level		= &pch_gpio_set2_level,
-		.reset		= &pch_gpio_set2_reset,
-	},
-	.set3 = {
-		.mode		= &pch_gpio_set3_mode,
-		.direction	= &pch_gpio_set3_direction,
-		.level		= &pch_gpio_set3_level,
-		.reset		= &pch_gpio_set3_reset,
-	},
-};
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c
deleted file mode 100644
index 0baeed019c..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	0x10ec0887,	/* Realtek ALC887 */
-	0x1458a002,	/* Subsystem ID */
-	15,		/* Number of 4 dword sets */
-	AZALIA_SUBVENDOR(2, 0x1458a002),
-	AZALIA_PIN_CFG(2, 0x11, 0x411110f0),
-	AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
-	AZALIA_PIN_CFG(2, 0x15, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x16, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x17, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
-	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
-	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
-	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
-	AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
-	AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),
-	AZALIA_PIN_CFG(2, 0x1f, 0x41c46060),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb
deleted file mode 100644
index 3672ba0007..0000000000
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/overridetree.cb
+++ /dev/null
@@ -1,57 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-## This file is part of the coreboot project.
-
-chip northbridge/intel/sandybridge
-	device domain 0 on
-
-		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-
-			device pci 1c.0 on  end	# RP #1: PCIe x1 Port (PCIEX1_3)
-			device pci 1c.1 on  end	# RP #2: PCIe x1 Port (PCIEX1_1)
-			device pci 1c.2 on  end	# RP #3: Etron EJ168 USB 3.0
-			device pci 1c.3 on  end	# RP #4: Marvell 88SE9172 SATA
-			device pci 1c.4 on  end	# RP #5: Realtek RTL8111F GbE NIC
-			device pci 1c.5 on  end	# RP #6: PCIe x1 Port (PCIEX1_2)
-
-			device pci 1f.0 on	# LPC bridge
-				chip superio/ite/it8728f
-					device pnp 2e.0 off end	# Floppy
-					device pnp 2e.1 off end	# COM1
-					device pnp 2e.2 off end	# COM2
-					device pnp 2e.3 off end	# Parallel port
-					device pnp 2e.4 on	# Environment Controller
-						io  0x60 = 0x0a30
-						io  0x62 = 0x0a20
-						irq 0x70 = 9
-						irq 0xf2 = 0x40
-					end
-					device pnp 2e.5 on	# Keyboard
-						io  0x60 = 0x60
-						io  0x62 = 0x64
-						irq 0x70 = 1
-						irq 0xf0 = 0x08
-					end
-					device pnp 2e.6 on	# Mouse
-						irq 0x70 = 12
-					end
-					device pnp 2e.7 on	# GPIO
-						irq 0x25 = 0x40
-						irq 0x26 = 0xf7
-						irq 0x27 = 0x10
-						irq 0x2c = 0x80
-						io  0x60 = 0x0000
-						io  0x62 = 0x0a00
-						io  0x64 = 0x0000
-						irq 0x70 = 0x00
-						irq 0x73 = 0x00
-						irq 0xcb = 0x00
-						irq 0xf0 = 0x10
-						irq 0xf1 = 0x40
-						irq 0xf6 = 0x1c
-					end
-					device pnp 2e.a off end	 # CIR
-				end
-			end
-		end
-	end
-end