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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-04 21:33:39 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-06 01:51:42 +0100
commit77757c22b9eede92234d07d65a23fdf4b970c8cf (patch)
tree29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src/mainboard/gigabyte/m57sli
parentd76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff)
downloadcoreboot-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.xz
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/gigabyte/m57sli')
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index b2e1d70477..da12a97c69 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -31,13 +31,13 @@
#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
+#include <northbridge/amd/amdk8/raminit.h>
#include "lib/delay.c"
-#include "cpu/x86/lapic.h"
+#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h>
#include <superio/ite/it8716f/it8716f.h>
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/nvidia/mcp55/early_ctrl.c"
@@ -61,9 +61,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-#include "southbridge/nvidia/mcp55/early_setup_ss.h"
+#include <southbridge/nvidia/mcp55/early_setup_ss.h>
#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "northbridge/amd/amdk8/f.h"
+#include <northbridge/amd/amdk8/f.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"