summaryrefslogtreecommitdiff
path: root/src/mainboard/gigabyte/m57sli
diff options
context:
space:
mode:
authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2007-11-14 17:57:04 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2007-11-14 17:57:04 +0000
commite13abe53b49fdd61fcf56bc21b578057c5f1c72f (patch)
tree4c78dbeae293d155ff5fd75a736c397387a5edb3 /src/mainboard/gigabyte/m57sli
parent34153ac0b8ef4d99de1d56b0e8733ae124f2ba0b (diff)
downloadcoreboot-e13abe53b49fdd61fcf56bc21b578057c5f1c72f.tar.xz
Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal.
Reason: The existing code does not tell us why it sets the watchdog clock at all, but since it appears in cache_as_ram_auto.c instead of the usual place (Config.lb) there has to be some meaning to it. Simply do what the proprietary bios does: Use the external clock source. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte/m57sli')
-rw-r--r--src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
index 30e2e69ace..86bb594c94 100644
--- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -273,8 +273,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
pnp_enter_ext_func_mode(SERIAL_DEV);
- /* The following line will set CLKIN to 24 MHz */
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 1);
+ /* The following line will set CLKIN to 24 MHz, external */
+ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
/* Is serial flash enabled? Then enable writing to serial flash. */
if (tmp & 0x0e) {