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author | Alec Ari <neotheuser@ymail.com> | 2012-04-23 20:12:30 -0500 |
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committer | Peter Stuge <peter@stuge.se> | 2012-04-24 03:57:45 +0200 |
commit | 8a527cfb49a15a08baffb7fbd6fdc51dbc28e9df (patch) | |
tree | 6e193bc980be454ec983e0a38800f3241cc6c17c /src/mainboard/gigabyte/ma785gm/romstage.c | |
parent | 1d89f14355e72d6969c8b8aae56904ebee965d43 (diff) | |
download | coreboot-8a527cfb49a15a08baffb7fbd6fdc51dbc28e9df.tar.xz |
Update MA785GM code
This commit adds the following to MA785GM:
Refactor some alignment handling
Unify Local APIC address definitions
ACPI: More ../../.. removal
Remove old AMD fam10 fixme comment
amd/sb700: Move HAVE_HARD_RESET to southbridge
Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/922
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/mainboard/gigabyte/ma785gm/romstage.c')
-rw-r--r-- | src/mainboard/gigabyte/ma785gm/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4572169b87..68f3dcc3b1 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } |