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author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-07-18 13:09:12 +0300 |
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committer | Martin Roth <martinroth@google.com> | 2019-07-21 18:53:21 +0000 |
commit | 3820e3ceed02d21900a060b2c70a031c34cae20d (patch) | |
tree | 4160ea25f657b868fc7fa18732d9b69acea80e58 /src/mainboard/gigabyte/ma785gmt/devicetree.cb | |
parent | f357f7e264baf35f98e216ac59abe71770147f40 (diff) | |
download | coreboot-3820e3ceed02d21900a060b2c70a031c34cae20d.tar.xz |
soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*
According to the documentation [1], by default the RX Level/Edge Trig
Configuration set to disable (2h = Drive '0') for each pad. Since this
setting doesn't matter for the GPO pad, there is no need to change the
default value for such pads. The patch updates PAD_CFG_GPO* macros to
set trig to disable. It also resolves some problems of creating the
PCH/SoC pads configuration based on information from the inteltool
dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
https://www.intel.com/content/dam/www/public/us/en/documents/
datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/34337
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/gigabyte/ma785gmt/devicetree.cb')
0 files changed, 0 insertions, 0 deletions