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authorDamien Zammit <damien@zamaudio.com>2016-11-28 00:29:10 +1100
committerMartin Roth <martinroth@google.com>2017-01-04 18:56:01 +0100
commit75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch)
tree618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/mainboard/gigabyte/ma785gmt
parent6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff)
downloadcoreboot-75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7.tar.xz
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/mainboard/gigabyte/ma785gmt')
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c36
1 files changed, 17 insertions, 19 deletions
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 860b1f1070..bf51e38238 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -27,43 +27,41 @@
#include <console/console.h>
#include <timestamp.h>
#include <cpu/amd/model_10xxx_rev.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdfam10/reset_test.c"
#include <commonlib/loglevel.h>
#include <cpu/x86/bist.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8718f/it8718f.h>
#include <cpu/amd/mtrr.h>
-#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/early_setup.c"
+#include <cpu/amd/car.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
-#include "northbridge/amd/amdfam10/debug.c"
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdht/ht_wrapper.h>
+#include <cpu/amd/family_10h-family_15h/init_cpus.h>
+#include <arch/early_variables.h>
+#include <cbmem.h>
+#include <spd.h>
+#include "southbridge/amd/rs780/early_setup.c"
+
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
+void activate_spd_rom(const struct mem_controller *ctrl);
+int spd_read_byte(unsigned device, unsigned address);
+extern struct sys_info sysinfo_car;
+
+void activate_spd_rom(const struct mem_controller *ctrl) { }
-static int spd_read_byte(u32 device, u32 address)
+int spd_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-#include <northbridge/amd/amdfam10/amdfam10.h>
-#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/pci.c"
-#include "resourcemap.c"
-#include "cpu/amd/quadcore/quadcore.c"
-#include <cpu/amd/microcode.h>
-
-#include "cpu/amd/family_10h-family_15h/init_cpus.c"
-#include "northbridge/amd/amdfam10/early_ht.c"
-#include <spd.h>
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;