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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-12 05:02:58 +1000 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-12 17:43:46 +0200 |
| commit | 2e4dea663ce9f23f8cd925803b045259219d927d (patch) | |
| tree | a59f1b7b5defa2c699c725ab368c31d69d8989db /src/mainboard/gigabyte/ma785gmt | |
| parent | f29200240e428761827ab8d179fa23068bfa9d59 (diff) | |
| download | coreboot-2e4dea663ce9f23f8cd925803b045259219d927d.tar.xz | |
superio/ite/it8718f: Remove hard coding from romstage
Make use of the ITE common Super I/O framework and there-by removing any
hard coding of Super I/O base address.
Change-Id: I14af89d2727d7c6bac0f9840043c430726297429
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5717
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/gigabyte/ma785gmt')
| -rw-r--r-- | src/mainboard/gigabyte/ma785gmt/romstage.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 451cb7956c..62a9211c1d 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |