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| author | Wang Qing Pei <wangqingpei@gmail.com> | 2010-11-09 09:09:47 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-09-04 12:22:00 +0200 |
| commit | f6e37316d0f751844898e92745182be9104d7df2 (patch) | |
| tree | e547df3d2278b974d25fd7b95ef3b9b9e10a7ebd /src/mainboard/gigabyte/ma78gm | |
| parent | 0e8ee81edbc3215d5f14cc80aef6dc08ee9d9f40 (diff) | |
| download | coreboot-f6e37316d0f751844898e92745182be9104d7df2.tar.xz | |
Disable dev3 on ma78gm-us2h
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.
Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/187
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/gigabyte/ma78gm')
| -rw-r--r-- | src/mainboard/gigabyte/ma78gm/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 1aa859f8a3..2fb4824c56 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -13,7 +13,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606 |