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authorStefan Reinauer <stepan@coresystems.de>2010-03-31 14:47:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-31 14:47:43 +0000
commit64ed2b73451de4b655b3fdda0ff42825a165c317 (patch)
tree0faaae313a9a9edbf8b33f56fc18830ba14aa75f /src/mainboard/gigabyte
parent5a1f5970857a5ad1fda0cf9d5945192408bf537b (diff)
downloadcoreboot-64ed2b73451de4b655b3fdda0ff42825a165c317.tar.xz
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c2
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c8
-rw-r--r--src/mainboard/gigabyte/m57sli/ap_romstage.c2
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c8
4 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
index d0a5eeb351..e42a312400 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
@@ -84,7 +84,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index d66bf51f59..7a0d910884 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -215,7 +215,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -241,7 +241,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
@@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
@@ -265,7 +265,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c
index 2bd3205842..28f47597e9 100644
--- a/src/mainboard/gigabyte/m57sli/ap_romstage.c
+++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c
@@ -82,7 +82,7 @@ void hardwaremain(int ret_addr)
id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 9ac67e465f..964e8048b3 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -228,7 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -254,7 +254,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
@@ -268,7 +268,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
@@ -279,7 +279,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);