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authorArthur Heymans <arthur@aheymans.xyz>2016-11-30 18:40:38 +0100
committerNico Huber <nico.h@gmx.de>2017-02-17 23:44:06 +0100
commit97e13d84c30c308c3b2bc629b38e6bcc9565dc3a (patch)
treee177a3c3b2cb9804767d7bbee0cb735ddc001246 /src/mainboard/gigabyte
parent17335fab175ed1a16f61729b03c1fbeeec366f37 (diff)
downloadcoreboot-97e13d84c30c308c3b2bc629b38e6bcc9565dc3a.tar.xz
nb/intel/x4x: Fix raminit on reset path
Previously the raminit failed on hot reset and to work around this issue it unconditionally did a cold reset. This has the following issues: * it's slow; * when the OS issues a hot reset some disk drives expect their 5V power supply to remain on, which gets cut off by a cold reset, causing data corruption. To fix this some steps in raminit must be ommited on the reset path. This includes receive enable calibration. To achieve this it stores receive enable results in RTC nvram for them to be rewritten on the resume path. Note: The same thing needs to be done on the S3 resume path. Calling a hot reset after raminit "outb(0x6, 0cf9)" works. Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18009 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout1
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c7
2 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
index 3138479092..fac9d3594d 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
@@ -68,6 +68,7 @@ entries
# coreboot config options: check sums
984 16 h 0 check_sum
+1024 144 r 0 recv_enable_results
# -----------------------------------------------------------------
enumerations
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 0f437951e5..d76fbb2434 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -30,6 +30,7 @@
#include <lib.h>
#include <arch/stages.h>
#include <cbmem.h>
+#include <northbridge/intel/x4x/iomap.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
@@ -130,6 +131,7 @@ void mainboard_romstage_entry(unsigned long bist)
{
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+ u8 boot_path = 0;
/* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
@@ -149,8 +151,11 @@ void mainboard_romstage_entry(unsigned long bist)
x4x_early_init();
+ if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
+ boot_path = BOOT_PATH_WARM_RESET;
+
printk(BIOS_DEBUG, "Initializing memory\n");
- sdram_initialize(0, spd_addrmap);
+ sdram_initialize(boot_path, spd_addrmap);
quick_ram_check();
cbmem_initialize_empty();
printk(BIOS_DEBUG, "Memory initialized\n");