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authorArthur Heymans <arthur@aheymans.xyz>2017-08-15 20:59:09 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-01-14 21:43:25 +0000
commitb451df2f400ba12fff440247330f8b57a93034bd (patch)
tree8bb52821a42aaaea2e614910d97b1ae4e690b7c2 /src/mainboard/gigabyte
parente4a016ff17b455a8acd0ea72b30caabb622ce224 (diff)
downloadcoreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.xz
mb/*/*/romstage.c: Clean up targets with i82801gx
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c24
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c31
2 files changed, 28 insertions, 27 deletions
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 9789d2acf6..926a5a7f36 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -68,27 +68,29 @@ static void setup_sio(void)
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
// Set COM1/COM2 decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
// Enable COM1
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+ | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMA_LPC_EN);
// Enable SuperIO Power Management Events
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
/* LPC decode range 2: Environment Controller */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040291);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
}
static void rcba_config(void)
{
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
+ RCBA8(OIC) = 0x03;
/* Disable unused devices */
- RCBA32(0x3418) = 0x003c0061;
+ RCBA32(FD) = 0x003c0061;
/* Enable PCIe Root Port Clock Gate */
- RCBA32(0x341c) = 0x00000001;
+ RCBA32(CG) = 0x00000001;
}
static void early_ich7_init(void)
@@ -123,14 +125,14 @@ static void early_ich7_init(void)
RCBA32(0x0214) = 0x10030509;
RCBA32(0x0218) = 0x00020504;
RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(0x3410);
+ reg32 = RCBA32(GCS);
reg32 |= (1 << 6);
- RCBA32(0x3410) = reg32;
+ RCBA32(GCS) = reg32;
reg32 = RCBA32(0x3430);
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
- RCBA32(0x3418) |= (1 << 0);
+ RCBA32(FD) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index e71e00cf52..ac336e45f7 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -89,23 +89,23 @@ static void mb_gpio_init(void)
ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
/* IRQ routing */
- RCBA32(0x3100) = 0x00002210;
- RCBA32(0x3104) = 0x00002100;
- RCBA32(0x3108) = 0x10004321;
- RCBA32(0x310c) = 0x00214321;
- RCBA32(0x3110) = 0x00000001;
- RCBA32(0x3140) = 0x00410032;
- RCBA32(0x3144) = 0x32100237;
- RCBA32(0x3148) = 0x00000000;
+ RCBA32(D31IP) = 0x00002210;
+ RCBA32(D30IP) = 0x00002100;
+ RCBA32(D29IP) = 0x10004321;
+ RCBA32(D28IP) = 0x00214321;
+ RCBA32(D27IP) = 0x00000001;
+ RCBA32(D31IR) = 0x00410032;
+ RCBA32(D29IR) = 0x32100237;
+ RCBA32(D27IR) = 0x00000000;
/* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
- RCBA8(0x31ff);
+ RCBA8(OIC) = 0x03;
+ RCBA8(OIC);
- RCBA32(0x3410) = 0x00190464;
+ RCBA32(GCS) = 0x00190464;
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
| FD_ACAUD | 1;
- RCBA32(0x341c) = 0x00000000;
+ RCBA32(CG) = 0x00000000;
RCBA32(0x3430) = 0x00000001;
RCBA32(0x3e00) = 0xff000001;
RCBA32(0x3e08) = 0x00000080;
@@ -119,15 +119,14 @@ static void mb_gpio_init(void)
static void ich7_enable_lpc(void)
{
/* Disable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
/* Decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN
| LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);
}
void mainboard_romstage_entry(unsigned long bist)