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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-25 09:03:55 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-25 09:03:55 +0000
commitdf323fcefd6020f8f418a13d65a075d282eed3de (patch)
tree1a7180ff77784fca47bb25785aad7a8b7db9dadb /src/mainboard/gigabyte
parent48ae6086da64eb260c6eed676c593cdcd0957fbf (diff)
downloadcoreboot-df323fcefd6020f8f418a13d65a075d282eed3de.tar.xz
MCP55: Add TINY_BOOTBLOCK support.
Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make the build work (but this is a good idea anyway, as it's used in multiple files). Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 968e384021..b76da5533f 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -81,7 +81,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -124,7 +123,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- mcp55_enable_rom();
}
if (bist == 0)