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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-07 20:10:28 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-08-23 03:36:05 +0000
commit714709fde638acdaa31b8e49b1f12c43f3f6b3d6 (patch)
treed9eeebb5a161a0f46870f846656838de91e2e982 /src/mainboard/gigabyte
parent390ba044dcd650e37340f1ddee98bedf1096e76d (diff)
downloadcoreboot-714709fde638acdaa31b8e49b1f12c43f3f6b3d6.tar.xz
AMD fam10 ACPI: Use common fixed sleepstates.asl
SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Note that all boards incorrectly had SSFG == 0x0D that previously enabled ACPI S3 sleep state even when it was not available. Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ma785gm/dsdt.asl24
-rw-r--r--src/mainboard/gigabyte/ma785gmt/dsdt.asl24
-rw-r--r--src/mainboard/gigabyte/ma78gm/dsdt.asl24
3 files changed, 3 insertions, 69 deletions
diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl
index 950eeea383..09f8a921ca 100644
--- a/src/mainboard/gigabyte/ma785gm/dsdt.asl
+++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl
@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})
diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl
index 950eeea383..09f8a921ca 100644
--- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl
+++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl
@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})
diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl
index 950eeea383..09f8a921ca 100644
--- a/src/mainboard/gigabyte/ma78gm/dsdt.asl
+++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl
@@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
- Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-
/* USB overcurrent mapping pins. */
Name(UOM0, 0)
Name(UOM1, 2)
@@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */
-
- /* Supported sleep states: */
- Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
- If (LAnd(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
- }
- If (LAnd(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
- }
- If (LAnd(SSFG, 0x04)) {
- Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
- }
- If (LAnd(SSFG, 0x08)) {
- Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
- }
-
- Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
-
- Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
- Name(CSMS, 0) /* Current System State */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
/* Wake status package */
Name(WKST,Package(){Zero, Zero})