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authorPaul Menzel <pmenzel@molgen.mpg.de>2016-07-28 17:20:20 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 18:44:00 +0200
commit95fe8fb1e0ce2ccf2d079898c27c799e4b0db928 (patch)
tree146616d6cc75ce8a4c2fbb10ee4084aa764d2a0a /src/mainboard/gigabyte
parent14caed85e121ca623d0ec4b9fba6d5bb64c8c46b (diff)
downloadcoreboot-95fe8fb1e0ce2ccf2d079898c27c799e4b0db928.tar.xz
mainboard: Format irq_tables.c
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c156
-rw-r--r--src/mainboard/gigabyte/m57sli/irq_tables.c77
-rw-r--r--src/mainboard/gigabyte/ma785gm/irq_tables.c3
-rw-r--r--src/mainboard/gigabyte/ma785gmt/irq_tables.c3
-rw-r--r--src/mainboard/gigabyte/ma78gm/irq_tables.c3
5 files changed, 126 insertions, 116 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
index d724a51191..abaaca21f5 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
@@ -25,24 +25,27 @@
#include <device/pci_ids.h>
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
+ uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+ uint8_t link1, uint16_t bitmap1, uint8_t link2,
+ uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
+ uint8_t slot, uint8_t rfu)
{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
}
-extern unsigned char bus_sis966[8]; //1
+
+extern unsigned char bus_sis966[8]; //1
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -53,24 +56,24 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t *v;
unsigned sbdn;
- uint8_t sum=0;
- int i;
+ uint8_t sum = 0;
+ int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
- /* This table must be between 0xf0000 & 0x100000 */
+ /* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
- v = (uint8_t *)(addr);
+ v = (uint8_t *) (addr);
pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
+ pirq->version = PIRQ_VERSION;
pirq->rtr_bus = 0;
pirq->rtr_devfn = PCI_DEVFN(2, 0);
@@ -84,11 +87,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
memset(pirq->rfu, 0, sizeof(pirq->rfu));
- pirq_info = (void *) ( &pirq->checksum + 1);
+ pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
- write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8,
+ 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++;
+ slot_num++;
pirq->size = 32 + 16 * slot_num;
@@ -103,56 +108,61 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_INFO, "done.\n");
- {
- device_t dev;
- dev = dev_find_slot(0, PCI_DEVFN(2,0));
+ {
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(2, 0));
if (dev) {
- /* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
-
- PINTA = IRQ10
- PINTB = IRQ11
- PINTC = NA
- PINTD = IRQ10
- PINTE = IRQ11
- PINTF = IRQ5
- PINTG = NA
- PINTH = IRQ7
-
- */
- uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63};
- uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
-
- for(i=0;i<8;i++)
- pci_write_config8(dev, reg[i], irq[i]);
- } // endif
-
- printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
-
- dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE)
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1
- pci_write_config8(dev, 0x3C, 0x0B);
- dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1
- pci_write_config8(dev, 0x3C, 0x05);
- dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0
+ /* initialize PCI interupts - these assignments depend
+ on the PCB routing of PINTA-D
+
+ PINTA = IRQ10
+ PINTB = IRQ11
+ PINTC = NA
+ PINTD = IRQ10
+ PINTE = IRQ11
+ PINTF = IRQ5
+ PINTG = NA
+ PINTH = IRQ7
+
+ */
+ uint8_t reg[8] = {
+ 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63
+ };
+ uint8_t irq[8] = {
+ 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07
+ };
+
+ for (i = 0; i < 8; i++)
+ pci_write_config8(dev, reg[i], irq[i]);
+ } // endif
+
+ printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
+
+ dev = dev_find_slot(0, PCI_DEVFN(2, 5)); // 5513 (IDE)
+ pci_write_config8(dev, 0x3C, 0x0A);
+ dev = dev_find_slot(0, PCI_DEVFN(3, 0)); // USB 1.1
+ pci_write_config8(dev, 0x3C, 0x0B);
+ dev = dev_find_slot(0, PCI_DEVFN(3, 1)); // USB 1.1
+ pci_write_config8(dev, 0x3C, 0x05);
+ dev = dev_find_slot(0, PCI_DEVFN(3, 3)); // USB 2.0
pci_write_config8(dev, 0x3C, 0x07);
- dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN)
+ dev = dev_find_slot(0, PCI_DEVFN(4, 0)); // 191 (LAN)
+ pci_write_config8(dev, 0x3C, 0x0A);
+ dev = dev_find_slot(0, PCI_DEVFN(5, 0)); // 1183 (SATA)
+ pci_write_config8(dev, 0x3C, 0x0B);
+ dev = dev_find_slot(0, PCI_DEVFN(6, 0)); // PCI-E
pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA)
- pci_write_config8(dev, 0x3C, 0x0B);
- dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E
- pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia
- pci_write_config8(dev, 0x3C, 0x05);
- }
+ dev = dev_find_slot(0, PCI_DEVFN(7, 0)); // PCI-E
+ pci_write_config8(dev, 0x3C, 0x0A);
+ dev = dev_find_slot(0, PCI_DEVFN(15, 0)); // Azalia
+ pci_write_config8(dev, 0x3C, 0x05);
+ }
printk(BIOS_DEBUG, "pirq routing table, size=%d\n", pirq->size);
- for (i = 0; i < pirq->size; i+=4)
- printk(BIOS_DEBUG, "%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]);
+ for (i = 0; i < pirq->size; i += 4)
+ printk(BIOS_DEBUG, "%.2x%.2x%.2x%.2x\n", v[i + 3], v[i + 2],
+ v[i + 1], v[i]);
- return (unsigned long) pirq_info;
+ return (unsigned long)pirq_info;
}
diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c
index 7c717f1142..4d42d7495c 100644
--- a/src/mainboard/gigabyte/m57sli/irq_tables.c
+++ b/src/mainboard/gigabyte/m57sli/irq_tables.c
@@ -23,26 +23,27 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
+ uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+ uint8_t link1, uint16_t bitmap1, uint8_t link2,
+ uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
+ uint8_t slot, uint8_t rfu)
{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
}
-extern unsigned char bus_mcp55[8]; //1
-
+extern unsigned char bus_mcp55[8]; //1
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -53,27 +54,27 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t *v;
unsigned sbdn;
- uint8_t sum=0;
- int i;
+ uint8_t sum = 0;
+ int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn;
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
- /* This table must be between 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
- v = (uint8_t *)(addr);
+ v = (uint8_t *) (addr);
pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
+ pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_mcp55[0];
- pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+ pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
pirq->exclusive_irqs = 0;
@@ -84,25 +85,27 @@ unsigned long write_pirq_routing_table(unsigned long addr)
memset(pirq->rfu, 0, sizeof(pirq->rfu));
- pirq_info = (void *) ( &pirq->checksum + 1);
+ pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
//pci bridge
- write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
+ 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++;
+ slot_num++;
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
printk(BIOS_INFO, "done.\n");
- return (unsigned long) pirq_info;
+ return (unsigned long)pirq_info;
}
diff --git a/src/mainboard/gigabyte/ma785gm/irq_tables.c b/src/mainboard/gigabyte/ma785gm/irq_tables.c
index 8c613da67c..aff85b63ee 100644
--- a/src/mainboard/gigabyte/ma785gm/irq_tables.c
+++ b/src/mainboard/gigabyte/ma785gm/irq_tables.c
@@ -21,8 +21,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-
-
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
@@ -41,6 +39,7 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
+
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
diff --git a/src/mainboard/gigabyte/ma785gmt/irq_tables.c b/src/mainboard/gigabyte/ma785gmt/irq_tables.c
index 8c613da67c..aff85b63ee 100644
--- a/src/mainboard/gigabyte/ma785gmt/irq_tables.c
+++ b/src/mainboard/gigabyte/ma785gmt/irq_tables.c
@@ -21,8 +21,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-
-
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
@@ -41,6 +39,7 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
+
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
diff --git a/src/mainboard/gigabyte/ma78gm/irq_tables.c b/src/mainboard/gigabyte/ma78gm/irq_tables.c
index 8c613da67c..aff85b63ee 100644
--- a/src/mainboard/gigabyte/ma78gm/irq_tables.c
+++ b/src/mainboard/gigabyte/ma78gm/irq_tables.c
@@ -21,8 +21,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
-
-
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
@@ -41,6 +39,7 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
+
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;