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| author | Zheng Bao <zheng.bao@amd.com> | 2011-03-28 03:33:10 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-03-28 03:33:10 +0000 |
| commit | c3422235b14d97c16bd13113c522827d1cfda9b4 (patch) | |
| tree | b7812e2a63ea8d08db61d1a3520836a29a97bcf8 /src/mainboard/gigabyte | |
| parent | 98fcc09cf9955e24376d15f6fe13f02545547276 (diff) | |
| download | coreboot-c3422235b14d97c16bd13113c522827d1cfda9b4.tar.xz | |
SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.
Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ma785gmt/romstage.c | 10 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ma78gm/romstage.c | 10 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 7826661042..d80df62b4e 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -83,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); + sb7xx_51xx_pci_port80(); } post_code(0x30); @@ -96,14 +96,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); enable_rs780_dev8(); - sb700_lpc_init(); + sb7xx_51xx_lpc_init(); it8718f_enable_serial(0, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); - sb700_early_setup(); + sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); @@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); rs780_before_pci_init(); - sb700_before_pci_init(); + sb7xx_51xx_before_pci_init(); post_code(0x42); printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 15ae9024c5..77e73b8c75 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); + sb7xx_51xx_pci_port80(); } post_code(0x30); @@ -100,14 +100,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); enable_rs780_dev8(); - sb700_lpc_init(); + sb7xx_51xx_lpc_init(); it8718f_enable_serial(0, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); - sb700_early_setup(); + sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); @@ -223,7 +223,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); rs780_before_pci_init(); - sb700_before_pci_init(); + sb7xx_51xx_before_pci_init(); post_code(0x42); printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); |