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authorTorsten Duwe <duwe@lst.de>2007-10-31 00:49:38 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2007-10-31 00:49:38 +0000
commite7537f134d8484f3b8560e00a838bdacce4ea884 (patch)
tree2e403190a1b23c159b974c408eb111c4a9587953 /src/mainboard/gigabyte
parenta8e2a0b852a3594a0031c62b7a57f9c442eafec4 (diff)
downloadcoreboot-e7537f134d8484f3b8560e00a838bdacce4ea884.tar.xz
As started in
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html , but change all apparantly related values that differ on my board with legacy BIOS. This makes both PCI cards appear, as well as the firewire device TSB43AB23. * PCI 01:07.0 appears fully functional * PCI 01:08.0 (closer to the board edge) appears, but no interrupts * PCI 01:0a.0 (FireWire) untested Since none of these was even present without the patch I suggest to apply it. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Harald Gutmann <harald.gutmann@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
index c39f626d28..3a17ef2d2f 100644
--- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -134,10 +134,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define MCP55_PCI_E_X_0 0
#define MCP55_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */