sb/intel/i82801gx: Add common LPC decode code

Generic LPC decode ranges can now be set from the devicetree.

Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

4 files changed, 7 insertions, 31 deletions

diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index f7e8ccc9a6..ff5d57b39f 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -79,6 +79,9 @@ chip northbridge/intel/i945
 
 			register "p_cnt_throttling_supported" = "0"
 
+			register "gen1_dec" = "0x000c0801" # ???
+			register "gen2_dec" = "0x00040291" # Environment Controller
+
 			device pci 1b.0 on # High Definition Audio
 				ioapic_irq 2 INTA 0x10
 			end
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 3a2c86da87..9a9e9473e6 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -56,22 +56,6 @@ static void setup_sio(void)
 	ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
 }
 
-static void ich7_enable_lpc(void)
-{
-	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
-	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
-	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
-			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-			| COMA_LPC_EN);
-	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
-	/* LPC decode range 2: Environment Controller */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
-}
-
 static void rcba_config(void)
 {
 	/* Enable IOAPIC */
@@ -115,7 +99,7 @@ void mainboard_romstage_entry(void)
 	int s3resume = 0, boot_mode = 0;
 	enable_lapic();
 
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	/* Enable SuperIO PM */
 	setup_sio();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index 7045dbf8e1..13da3e8704 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -50,6 +50,8 @@ chip northbridge/intel/x4x		# Northbridge
       register "sata_ports_implemented" = "0x3"
       register "gpe0_en" = "0x40"
 
+      register "gen2_dec" = "0x007c0291" # HWM
+
       device pci 1b.0 on		# Audio
         subsystemid 0x1458 0xa002
       end
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 8ba173eec6..fa69d122cb 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -98,19 +98,6 @@ static void mb_gpio_init(void)
 	ich7_setup_cir();
 }
 
-static void ich7_enable_lpc(void)
-{
-	/* Disable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
-	/* Decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
-		CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN
-			| LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
-
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);
-}
-
 void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
@@ -119,7 +106,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich7_enable_lpc();
+	i82801gx_lpc_setup();
 	mb_gpio_init();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);