diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-01-26 17:24:48 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-29 00:29:30 +0100 |
| commit | 9253ce60c4bce74854938c22008829da48ae97a9 (patch) | |
| tree | e1f2f1607cd15e7272a1f96b21046b2709949acc /src/mainboard/gigabyte | |
| parent | c70966cd267783e2819418e5d881a2098c476d80 (diff) | |
| download | coreboot-9253ce60c4bce74854938c22008829da48ae97a9.tar.xz | |
mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.
Fixed incorrect comment regarding port 80 LPC route.
Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index ca8ca5c071..bff481f2d5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -58,21 +58,6 @@ static void mb_gpio_init(void) outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); outl(0x00000083, DEFAULT_GPIOBASE + 0x38); - /* Set default power management registers */ - pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); - outw(0x0011, DEFAULT_PMBASE + 0x00); - outw(0x0120, DEFAULT_PMBASE + 0x02); - outl(0x00001c01, DEFAULT_PMBASE + 0x04); - outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); - outl(0x000000a0, DEFAULT_PMBASE + 0x10); - outl(0xc5000000, DEFAULT_PMBASE + 0x28); - outl(0x00000040, DEFAULT_PMBASE + 0x2c); - outw(0x13e0, DEFAULT_PMBASE + 0x44); - outw(0x003f, DEFAULT_PMBASE + 0x60); - outw(0x0800, DEFAULT_PMBASE + 0x68); - outw(0x0008, DEFAULT_PMBASE + 0x6a); - outw(0x003f, DEFAULT_PMBASE + 0x72); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -137,8 +122,8 @@ void main(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - /* Disable watchdog timer and route port 80 to LPC */ - RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); |