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authorArthur Heymans <arthur@aheymans.xyz>2019-11-11 21:14:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-15 16:41:52 +0000
commitbf53acca5e9c6b61086e42eb9e73fd4bb59a6f31 (patch)
tree8c2319996bb91648bc9db77f6a9dc428164f6225 /src/mainboard/gigabyte
parentdc7b2de88bb56d3284c3ab6227cffefd8c76836b (diff)
downloadcoreboot-bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31.tar.xz
nb/intel/x4x: Move boilerplate romstage to a common location
This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c48
1 files changed, 9 insertions, 39 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 16b157b2dd..bde4f33bef 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -14,14 +14,9 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <console/console.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
-#include <arch/romstage.h>
#include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h>
@@ -34,7 +29,7 @@
* We should use standard gpio.h eventually
*/
-static void mb_lpc_init(void)
+void mb_lpc_setup(void)
{
pci_devfn_t dev;
@@ -73,6 +68,11 @@ static void mb_lpc_init(void)
ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Disable SIO reboot */
+ ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
+
/* IRQ routing */
RCBA32(D31IP) = 0x00002210;
RCBA32(D30IP) = 0x00002100;
@@ -84,38 +84,8 @@ static void mb_lpc_init(void)
RCBA32(D27IR) = 0x00000000;
}
-void mainboard_romstage_entry(void)
+void mb_get_spd_map(u8 spd_map[4])
{
- // ch0 ch1
- const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
- u8 boot_path = 0;
- u8 s3_resume;
-
- /* Set southbridge and Super I/O GPIOs. */
- i82801gx_lpc_setup();
- mb_lpc_init();
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- /* Disable SIO reboot */
- ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
-
- console_init();
-
- enable_smbus();
-
- i82801gx_early_init();
- x4x_early_init();
-
- s3_resume = southbridge_detect_s3_resume();
- if (s3_resume)
- boot_path = BOOT_PATH_RESUME;
- if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
- boot_path = BOOT_PATH_WARM_RESET;
-
- sdram_initialize(boot_path, spd_addrmap);
-
- x4x_late_init(s3_resume);
-
- printk(BIOS_DEBUG, "x4x late init complete\n");
-
+ spd_map[0] = 0x50;
+ spd_map[2] = 0x52;
}