diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-15 22:02:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-12 14:06:37 +0000 |
| commit | b9d2589ca40026b543ecb5b008ce0d1bc346bf53 (patch) | |
| tree | 87cac45cfc1c1211f012aaa76b8a87162f092aff /src/mainboard/gigabyte | |
| parent | 81dd52b7eb663c6098de5d8c7c56ed572c91b539 (diff) | |
| download | coreboot-b9d2589ca40026b543ecb5b008ce0d1bc346bf53.tar.xz | |
mb/*/*: Harmonise FD and devicetree on boards featuring ICH7
On some boards the devicetree and Function Disable register did not
match. In this case the FD values are put in the devicetree as these
were the values that were actually used in practice.
A complete devicetree will make it easier to automatically disable
devices in ramstage.
Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 9 |
3 files changed, 13 insertions, 9 deletions
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 6bdc134b9a..7ed4d199aa 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -86,10 +86,10 @@ chip northbridge/intel/i945 end device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe - #device pci 1c.2 off end # PCIe port 3 - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 + device pci 1c.2 off end # PCIe port 3 + device pci 1c.3 off end # PCIe port 4 + device pci 1c.4 off end # PCIe port 5 + device pci 1c.5 off end # PCIe port 6 device pci 1d.0 on # USB UHCI ioapic_irq 2 INTA 0x10 end @@ -106,6 +106,8 @@ chip northbridge/intel/i945 ioapic_irq 2 INTA 0x10 end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge ioapic_irq 2 INTA 0x10 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 4768885a5e..6ed5b2f740 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -85,7 +85,8 @@ static void rcba_config(void) RCBA8(OIC) = 0x03; /* Disable unused devices */ - RCBA32(FD) = 0x003c0061; + RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 + | FD_ACMOD | FD_ACAUD | 1; /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) = 0x00000001; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index d9483980d8..9f92d2adf5 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -62,7 +62,9 @@ chip northbridge/intel/x4x # Northbridge end end device pci 1c.2 on end # PCIe 3 - device pci 1c.3 on end # PCIe 4 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 device pci 1d.0 on # USB subsystemid 0x1458 0x5004 end @@ -79,6 +81,8 @@ chip northbridge/intel/x4x # Northbridge subsystemid 0x1458 0x5006 end device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1458 0x5001 chip superio/ite/it8718f # Super I/O @@ -164,9 +168,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.3 on # SMbus subsystemid 0x1458 0x5001 end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end end end end |