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| author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2012-10-26 19:01:45 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-10-26 21:55:17 +0200 |
| commit | 59e3e0299112070e51c4dabc8f616344e291956f (patch) | |
| tree | 2a95bed4cde51ccf777b50661ed32c3328ea7a3d /src/mainboard/gigabyte | |
| parent | 50dd47bb58bee2ed159c1c5f6eb51dd583094f26 (diff) | |
| download | coreboot-59e3e0299112070e51c4dabc8f616344e291956f.tar.xz | |
northbridge/sch: read the size of main memory from the proper register
I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c
but it is not written there. The size of memory is written in
src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for
"Setting up TOM").
Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1629
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/gigabyte')
0 files changed, 0 insertions, 0 deletions