summaryrefslogtreecommitdiff
path: root/src/mainboard/gigabyte
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-22 23:14:27 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-30 07:19:10 +0100
commit5c62375222997d62a796a521b9c8af521882dbe2 (patch)
treee0ca7c349e3c456a5a5540352a9cfefec693d012 /src/mainboard/gigabyte
parent7d3045b517907d0827d5800b1bfb399a3df5ada7 (diff)
downloadcoreboot-5c62375222997d62a796a521b9c8af521882dbe2.tar.xz
AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c2
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c2
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index f770577ddf..633daad09a 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -145,9 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 88f3d2558a..3fbaacb8b7 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -148,9 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();