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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-19 13:19:15 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-28 17:19:37 +0200 |
| commit | 8621a135d40c93445684f7b1e9c77d9aee392978 (patch) | |
| tree | 0836e7736671506fa07e161774bd2a9d7cc85389 /src/mainboard/gigabyte | |
| parent | 3eff00ec76f91f5dc9ddf39e2e6073f6053c94a1 (diff) | |
| download | coreboot-8621a135d40c93445684f7b1e9c77d9aee392978.tar.xz | |
sb/nvidia/mcp55: Link early_ctrl.c
Change-Id: I3a55c2e8077fdb10768df287f38efcd5e2e64bdf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19365
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index cdd6d432a0..a194ccd08d 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -67,7 +67,6 @@ int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include <northbridge/amd/amdk8/f.h> |