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authorTorsten Duwe <duwe@lst.de>2007-11-05 22:35:01 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2007-11-05 22:35:01 +0000
commitc931625babcfacda301598f4eb0cea37d6e0e08c (patch)
tree899bd30eb44e7a504abb996f919d443ac6599cfd /src/mainboard/gigabyte
parenta358892e2cd6f57c0645dc95120fd253d75e20b7 (diff)
downloadcoreboot-c931625babcfacda301598f4eb0cea37d6e0e08c.tar.xz
Fix the M57SLI routing table, as apparently set up from LinuxBIOS on
that board. Shift PCIe pin numbers downwards, and PCI int pins upwards. This puts both PCI slots' int A and PCIe 16x int A into the right position. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/m57sli/mptable.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 5a08e08231..749b630bb1 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -129,13 +129,13 @@ void *smp_write_config_table(void *v)
for(j=7; j>=2; j--) {
if(!bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (1+j+i)%4);
}
}
for(j=0; j<2; j++)
for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06+j)<<2)|i, apicid_mcp55, 0x10 + (2+i+j)%4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x07+j)<<2)|i, apicid_mcp55, 0x10 + (3+i+j)%4);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/