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| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-01 18:28:07 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-05 00:12:23 +0000 |
| commit | 0b707f6667451bdc1642717ae81e0ab1b24bee6c (patch) | |
| tree | a358221050c760b70f9f83886e6eaccda1a4f23b /src/mainboard/gigabyte | |
| parent | 39930b79c17af04a276662c8796f27323d15ba43 (diff) | |
| download | coreboot-0b707f6667451bdc1642717ae81e0ab1b24bee6c.tar.xz | |
mb/gigabyte/ga-b75m-d3h/devicetree.cb: Drop zero fields
They default to zero already.
Change-Id: I76bbf4593c43ce24c28568f1b8faefb1be81b4cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte')
| -rw-r--r-- | src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index b5a10fc66e..e581470daa 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -30,8 +30,6 @@ chip northbridge/intel/sandybridge end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - # GPI routing - register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x003c0a01" # Set max SATA speed to 6.0 Gb/s @@ -41,8 +39,6 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "pcie_port_coalesce" = "0" - register "docking_supported" = "0" register "c2_latency" = "0x0065" device pci 14.0 on # USB 3.0 Controller |