soc/mediatek: Use MRC cache API for asurada

Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.

This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.

Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.

With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none

Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

2 files changed, 2 insertions, 41 deletions

diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd
index 2635854866..7194632e36 100644
--- a/src/mainboard/google/asurada/chromeos.fmd
+++ b/src/mainboard/google/asurada/chromeos.fmd
@@ -29,7 +29,7 @@ FLASH@0x0 8M {
 	RW_MISC 36K {
 		RW_VPD(PRESERVE) 16K  # At least 8K.
 		RW_NVRAM(PRESERVE) 8K
-		RW_DDR_TRAINING(PRESERVE) 8K
+		RW_MRC_CACHE(PRESERVE) 8K
 		RW_ELOG(PRESERVE) 4K  # ELOG driver hard-coded size in 4K.
 	}
 	RW_SECTION_B 1500K {
diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c
index 0f88d2022d..4cd9b2abd3 100644
--- a/src/mainboard/google/asurada/romstage.c
+++ b/src/mainboard/google/asurada/romstage.c
@@ -1,13 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/stages.h>
-#include <console/console.h>
 #include <delay.h>
-#include <fmap.h>
 #include <soc/clkbuf.h>
-#include <soc/dramc_param.h>
 #include <soc/emi.h>
-#include <soc/mmu_operations.h>
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
 #include <soc/pll_common.h>
@@ -15,40 +11,6 @@
 #include <soc/rtc.h>
 #include <soc/srclken_rc.h>
 
-/* This must be defined in chromeos.fmd in same name and size. */
-#define CALIBRATION_REGION		"RW_DDR_TRAINING"
-#define CALIBRATION_REGION_SIZE		0x2000
-
-_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE,
-	       "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION);
-
-static bool read_calibration_data_from_flash(struct dramc_param *dparam)
-{
-	const size_t length = sizeof(*dparam);
-	size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length);
-	printk(BIOS_DEBUG, "read data from flash, ret=%#zx, length=%#zx\n", ret, length);
-
-	return ret == length;
-}
-
-static bool write_calibration_data_to_flash(const struct dramc_param *dparam)
-{
-	const size_t length = sizeof(*dparam);
-	size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length);
-	printk(BIOS_DEBUG, "write data from flash, ret=%#zx, length=%#zx\n", ret, length);
-
-	return ret == length;
-}
-
-/* dramc_param is ~2K and too large to fit in stack. */
-static struct dramc_param dramc_parameter;
-
-static struct dramc_param_ops dparam_ops = {
-	.param = &dramc_parameter,
-	.read_from_flash = &read_calibration_data_from_flash,
-	.write_to_flash = &write_calibration_data_to_flash,
-};
-
 static void raise_little_cpu_freq(void)
 {
 	mt6359p_buck_set_voltage(MT6359P_SRAM_PROC2, 1000 * 1000);
@@ -67,6 +29,5 @@ void platform_romstage_main(void)
 	clk_buf_init();
 	rtc_boot();
 	raise_little_cpu_freq();
-	mt_mem_init(&dparam_ops);
-	mtk_mmu_after_dram();
+	mtk_dram_init();
 }