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authorMarc Jones <marc.jones@se-eng.com>2015-06-09 21:18:38 -0600
committerMarc Jones <marc.jones@se-eng.com>2015-06-13 18:09:20 +0200
commitd862121fbe6285be2f91a0c09058a22a775c0d19 (patch)
tree4ef78f4c720e49a81303f81ccfa957d2fcd64bf1 /src/mainboard/google/auron/chromeos.c
parentf2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 (diff)
downloadcoreboot-d862121fbe6285be2f91a0c09058a22a775c0d19.tar.xz
google/auron: Add mainboard
Add the Google Auron Broadwell Reference Mainboard. It is based on the Google Peppy mainboard. It was merged from the following chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10500 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/chromeos.c')
-rw-r--r--src/mainboard/google/auron/chromeos.c36
1 files changed, 23 insertions, 13 deletions
diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c
index ef10c48997..a5e2aea1f4 100644
--- a/src/mainboard/google/auron/chromeos.c
+++ b/src/mainboard/google/auron/chromeos.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,16 +18,17 @@
*/
#include <string.h>
-#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-
-#if CONFIG_EC_GOOGLE_CHROMEEC
-#include "ec.h"
+#include <console/console.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#include <ec/google/chromeec/ec.h>
-#endif
+#include <soc/gpio.h>
+#include "ec.h"
+
+/* SPI Write protect is GPIO 16 */
+#define CROS_WP_GPIO 58
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -36,15 +37,24 @@
static int get_lid_switch(void)
{
-#if CONFIG_EC_GOOGLE_CHROMEEC
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
return !!(ec_switches & EC_SWITCH_LID_OPEN);
-#else
- return 0;
-#endif
}
+/*static void fill_lb_gpio(struct lb_gpio *gpio, int num,
+ int polarity, const char *name, int force)
+{
+ memset(gpio, 0, sizeof(*gpio));
+ gpio->port = num;
+ gpio->polarity = polarity;
+ if (force >= 0)
+ gpio->value = force;
+ else if (num >= 0)
+ gpio->value = get_gpio(num);
+ strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
+}
+*/
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio *gpio;
@@ -53,7 +63,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->count = GPIO_COUNT;
gpio = gpios->gpios;
- fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0);
+ fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
get_recovery_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
@@ -95,5 +105,5 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
- return get_gpio(58);
+ return get_gpio(CROS_WP_GPIO);
}