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authorAngel Pons <th3fanbus@gmail.com>2020-07-25 15:11:15 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-28 08:52:42 +0000
commit4a6c0a368e96e393ef48606d6be30bbd9aee2d36 (patch)
tree78a5de1d840a6332cdce71ef2d4e1e6b99b40564 /src/mainboard/google/auron/devicetree.cb
parent9f78127b61632cbb138bdbfa650c2e9965440d3b (diff)
downloadcoreboot-4a6c0a368e96e393ef48606d6be30bbd9aee2d36.tar.xz
broadwell: Factor out PIRQ routing from devicetree
All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is invalid and modern OSes don't use PIRQ routing, disable the PIRQs. Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/auron/devicetree.cb')
-rw-r--r--src/mainboard/google/auron/devicetree.cb9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 65d4ce9c47..a3097624fe 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -15,15 +15,6 @@ chip soc/intel/broadwell
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
- register "pirqa_routing" = "0x80"
- register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x80"
- register "pirqd_routing" = "0x80"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
-
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"