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authorMarc Jones <marc.jones@se-eng.com>2015-06-09 14:42:55 -0600
committerMarc Jones <marc.jones@se-eng.com>2015-06-10 20:14:04 +0200
commit07cf24c2eefc7d6f39061bad3400a403d7879481 (patch)
tree98037054729590350a9f069660c5115aa6dfd549 /src/mainboard/google/auron/dsdt.asl
parent36aed7474c77894ea8a3eca59991c57108d56e86 (diff)
downloadcoreboot-07cf24c2eefc7d6f39061bad3400a403d7879481.tar.xz
google/auron: Add initial mainboard copy from Peppy
Copy the Peppy directory. No changes. Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10499 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/dsdt.asl')
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diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl
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+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // CPU
+ #include <cpu/intel/haswell/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/haswell.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+ }
+
+ // Thermal handler
+ #include "acpi/thermal.asl"
+
+ // Chrome OS specific
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chipset specific sleep states
+ #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+}