Add/Combine Broadwell Chromebooks using variant board scheme

Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.

Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]

Additionally, some minor cleanup/changes were made:
 - I2C devices set to use level (vs edge) interrupt triggering
 - HDA verb entries use simplified macro entry format
 - correct FADT table header version
 - remove unused ACPI device entries / .asl file(s)
 - clean up ACPI code (e.g., trackpad on Lulu)
 - adjust _CID for trackpad on Lulu in order to not load non-functional
    Windows driver (does not affect Linux)
 - remove unused header includes (multiple/various)
 - correct I2C addresses used for SMBIOS device entries
 - correct misc typos etc

The existing auron_paine samus boards are removed.

Variant setup modeled after google/slippy

Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

19 files changed, 1090 insertions, 0 deletions

diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb
new file mode 100644
index 0000000000..9f086a6392
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb
@@ -0,0 +1,110 @@
+chip soc/intel/broadwell
+
+	# Enable eDP Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Disable DisplayPort C Hotplug
+	register "gpu_dp_c_hotplug" = "0x00"
+
+	# Enable HDMI Hotplug with 6ms pulse
+	register "gpu_dp_b_hotplug" = "0x06"
+
+	# Set backlight PWM values for eDP
+	register "gpu_cpu_backlight" = "0x00000200"
+	register "gpu_pch_backlight" = "0x04000000"
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
+	register "gpu_panel_power_up_delay" = "400"		# 40ms
+	register "gpu_panel_power_down_delay" = "150"		# 15ms
+	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
+
+	register "pirqa_routing" = "0x8b"
+	register "pirqb_routing" = "0x8a"
+	register "pirqc_routing" = "0x8b"
+	register "pirqd_routing" = "0x8b"
+	register "pirqe_routing" = "0x80"
+	register "pirqf_routing" = "0x80"
+	register "pirqg_routing" = "0x80"
+	register "pirqh_routing" = "0x80"
+
+	# EC range is 0x800-0x9ff
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x00fc0901"
+
+	# EC_SMI is GPIO34
+	register "alt_gp_smi_en" = "0x0004"
+	register "gpe0_en_1" = "0x00000000"
+	# EC_SCI is GPIO36
+	register "gpe0_en_2" = "0x00000010"
+	register "gpe0_en_3" = "0x00000000"
+	register "gpe0_en_4" = "0x00000000"
+
+	register "sata_port_map" = "0x1"
+	register "sata_devslp_disable" = "1"
+
+	register "sio_acpi_mode" = "1"
+
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x5"
+	register "sata_port1_gen3_dtle" = "0x5"
+
+	# Force enable ASPM for PCIe Port1
+	register "pcie_port_force_aspm" = "0x01"
+
+	# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
+	register "icc_clock_disable" = "0x013c0000"
+
+	register "s0ix_enable" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+		device pci 03.0 on end # mini-hd audio
+		device pci 13.0 off end # Smart Sound Audio DSP
+		device pci 14.0 on end # USB3 XHCI
+		device pci 15.0 on end # Serial I/O DMA
+		device pci 15.1 on end # I2C0
+		device pci 15.2 on end # I2C1
+		device pci 15.3 off end # GSPI0
+		device pci 15.4 off end # GSPI1
+		device pci 15.5 off end # UART0
+		device pci 15.6 off end # UART1
+		device pci 16.0 on end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT
+		device pci 17.0 off end # SDIO
+		device pci 19.0 off end # GbE
+		device pci 1b.0 on end # High Definition Audio
+		device pci 1c.0 on end # PCIe Port #1
+		device pci 1c.1 off end # PCIe Port #2
+		device pci 1c.2 off end # PCIe Port #3
+		device pci 1c.3 off end # PCIe Port #4
+		device pci 1c.4 off end # PCIe Port #5
+		device pci 1c.5 off end # PCIe Port #6
+		device pci 1d.0 on end # USB2 EHCI
+		device pci 1e.0 off end # PCI bridge
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				# Rising edge interrupt
+				register "irq_polarity" = "2"
+				device pnp 0c31.0 on
+					irq 0x70 = 10
+				end
+			end
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC bridge
+		device pci 1f.2 on end # SATA Controller
+		device pci 1f.3 off end # SMBus
+		device pci 1f.6 on end # Thermal
+	end
+end
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..1f91456d77
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/mainboard.asl
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.I2C0)
+{
+	Device (STPA)
+	{
+		Name (_HID, "SYNA0000")
+		Name (_CID, "ACPI0C50")
+		Name (_DDN, "Synaptics Touchpad")
+		Name (_UID, 1)
+		Name (ISTP, 1) /* Touchpad */
+
+		Method(_CRS, 0x0, Serialized)
+		{
+			Name (RBUF, ResourceTemplate()
+			{
+				I2cSerialBus (
+					BOARD_TRACKPAD_I2C_ADDR,	// SlaveAddress
+					ControllerInitiated,		// SlaveMode
+					400000,				// ConnectionSpeed
+					AddressingMode7Bit,		// AddressingMode
+					"\\_SB.PCI0.I2C0",		// ResourceSource
+				)
+				Interrupt (ResourceConsumer, Level, ActiveLow)
+				{
+					BOARD_TRACKPAD_IRQ
+				}
+			})
+			Return(RBUF)
+		}
+
+		Method(_DSM, 0x4, NotSerialized)
+		{
+			If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) /* I2C-HID UUID */
+			{
+				If (LEqual(Arg2, Zero)) /* DSM Function */
+				{
+					/* Function 0: Query function, return based on revision */
+					If (LEqual(Arg1, One)) /* Arg1 DSM Revision */
+					{
+						/* Revision 1: Function 0 supported */
+						Return(Buffer(One) { 0x03 })
+					}
+				} ElseIf (LEqual(Arg2, One)) /* Function 1 : HID Function */
+				{
+					Return(0x0020) /* HID Descriptor Address */
+				}
+			}
+
+			Return(Buffer(One) { 0x00 }) /* Not supported */
+		}
+
+		Method (_STA)
+		{
+			If (LEqual (\S1EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+		Method (_DSW, 3, NotSerialized)
+		{
+			Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+			If (LEqual (Arg0, 1)) {
+				// Enable GPIO as wake source
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+			}
+		}
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
+Scope (\_SB.PCI0.I2C1)
+{
+	Device (ETSA)
+	{
+		Name (_HID, "ELAN0001")
+		Name (_DDN, "Elan Touchscreen")
+		Name (_UID, 6)
+		Name (ISTP, 0) /* Touchscreen */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHSCREEN_I2C_ADDR,	// SlaveAddress
+				ControllerInitiated,		// SlaveMode
+				400000,				// ConnectionSpeed
+				AddressingMode7Bit,		// AddressingMode
+				"\\_SB.PCI0.I2C1",		// ResourceSource
+			)
+			Interrupt (ResourceConsumer, Level, ActiveLow)
+			{
+				BOARD_TOUCHSCREEN_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+			If (LEqual (\S2EN, 1)) {
+				Return (0xF)
+			} Else {
+				Return (0x0)
+			}
+		}
+
+		Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+		Method (_DSW, 3, NotSerialized)
+		{
+			Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
+			If (LEqual (Arg0, 1)) {
+				// Enable GPIO as wake source
+				\_SB.PCI0.LPCB.GPIO.GWAK (Local0)
+			}
+		}
+
+		/* Allow device to power off in S0 */
+		Name (_S0W, 4)
+	}
+}
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h b/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h
new file mode 100644
index 0000000000..726dcc755e
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Sage Electronic Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef LULU_GPIO_H
+#define LULU_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_UNUSED,        /* 0: UNUSED */
+	PCH_GPIO_UNUSED,        /* 1: UNUSED */
+	PCH_GPIO_UNUSED,        /* 2: UNUSED */
+	PCH_GPIO_UNUSED,        /* 3: UNUSED */
+	PCH_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	PCH_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	PCH_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	PCH_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	PCH_GPIO_INPUT,         /* 8: RAM_ID4 */
+	PCH_GPIO_INPUT,         /* 9: RAM_ID1 */
+	PCH_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	PCH_GPIO_UNUSED,        /* 11: UNUSED */
+	PCH_GPIO_INPUT_INVERT,  /* 12: TRACKPAD_INT_L (WAKE) */
+	PCH_GPIO_INPUT,         /* 13: RAM_ID0 */
+	PCH_GPIO_INPUT,         /* 14: EC_IN_RW */
+	PCH_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 16: UNUSED */
+	PCH_GPIO_UNUSED,        /* 17: UNUSED */
+	PCH_GPIO_NATIVE,        /* 18: PCIE_CLKREQ_WLAN# */
+	PCH_GPIO_UNUSED,        /* 19: UNUSED */
+	PCH_GPIO_UNUSED,        /* 20: UNUSED */
+	PCH_GPIO_UNUSED,        /* 21: UNUSED */
+	PCH_GPIO_UNUSED,        /* 22: UNUSED */
+	PCH_GPIO_UNUSED,        /* 23: UNUSED */
+	PCH_GPIO_UNUSED,        /* 24: UNUSED */
+	PCH_GPIO_INPUT_INVERT,  /* 25: TOUCH_INT_L (WAKE) */
+	PCH_GPIO_UNUSED,        /* 26: UNUSED */
+	PCH_GPIO_UNUSED,        /* 27: UNUSED */
+	PCH_GPIO_UNUSED,        /* 28: UNUSED */
+	PCH_GPIO_UNUSED,        /* 29: UNUSED */
+	PCH_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSWARN_L */
+	PCH_GPIO_NATIVE,        /* 31: NATIVE: ACPRESENT */
+	PCH_GPIO_NATIVE,        /* 32: NATIVE: LPC_CLKRUN_L */
+	PCH_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	PCH_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	PCH_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	PCH_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	PCH_GPIO_UNUSED,        /* 37: UNUSED */
+	PCH_GPIO_UNUSED,        /* 38: UNUSED */
+	PCH_GPIO_UNUSED,        /* 39: UNUSED */
+	PCH_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	PCH_GPIO_UNUSED,        /* 41: UNUSED */
+	PCH_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	PCH_GPIO_UNUSED,        /* 43: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 44: PP3300_SSD_EN */
+	PCH_GPIO_OUT_HIGH,      /* 45: PP3300_CODEC_EN */
+	PCH_GPIO_OUT_HIGH,      /* 46: WLAN_DISABLE_L */
+	PCH_GPIO_INPUT,         /* 47: RAM_ID2 */
+	PCH_GPIO_UNUSED,        /* 48: UNUSED */
+	PCH_GPIO_UNUSED,        /* 49: UNUSED */
+	PCH_GPIO_UNUSED,        /* 50: UNUSED */
+	PCH_GPIO_UNUSED,        /* 51: UNUSED */
+	PCH_GPIO_UNUSED,        /* 52: UNUSED */
+	PCH_GPIO_PIRQ,          /* 53: TRACKPAD_INT_DX */
+	PCH_GPIO_PIRQ,          /* 54: TOUCH_INT_L_DX */
+	PCH_GPIO_UNUSED,        /* 55: UNUSED */
+	PCH_GPIO_UNUSED,        /* 56: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 57: PP3300_CCD_EN */
+	PCH_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	PCH_GPIO_UNUSED,        /* 59: UNUSED */
+	PCH_GPIO_NATIVE,        /* 60: NATIVE: SML0ALERT */
+	PCH_GPIO_UNUSED,        /* 61: UNUSED */
+	PCH_GPIO_UNUSED,        /* 62: UNUSED */
+	PCH_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	PCH_GPIO_UNUSED,        /* 64: UNUSED */
+	PCH_GPIO_UNUSED,        /* 65: UNUSED */
+	PCH_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 67: UNUSED */
+	PCH_GPIO_UNUSED,        /* 68: UNUSED */
+	PCH_GPIO_UNUSED,        /* 69: UNUSED */
+	PCH_GPIO_UNUSED,        /* 70: UNUSED */
+	PCH_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	PCH_GPIO_NATIVE,        /* 72: NATIVE: PCH_BATLOW# */
+	PCH_GPIO_NATIVE,        /* 73: NATIVE: SMB1ALERT# */
+	PCH_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	PCH_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	PCH_GPIO_UNUSED,        /* 76: UNUSED */
+	PCH_GPIO_UNUSED,        /* 77: UNUSED */
+	PCH_GPIO_UNUSED,        /* 78: UNUSED */
+	PCH_GPIO_UNUSED,        /* 79: UNUSED */
+	PCH_GPIO_UNUSED,        /* 80: UNUSED */
+	PCH_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	PCH_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	PCH_GPIO_UNUSED,        /* 83: UNUSED */
+	PCH_GPIO_UNUSED,        /* 84: UNUSED */
+	PCH_GPIO_UNUSED,        /* 85: UNUSED */
+	PCH_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 87: UNUSED */
+	PCH_GPIO_UNUSED,        /* 88: UNUSED */
+	PCH_GPIO_UNUSED,        /* 89: UNUSED */
+	PCH_GPIO_UNUSED,        /* 90: UNUSED */
+	PCH_GPIO_UNUSED,        /* 91: UNUSED */
+	PCH_GPIO_UNUSED,        /* 92: UNUSED */
+	PCH_GPIO_UNUSED,        /* 93: UNUSED */
+	PCH_GPIO_UNUSED,        /* 94: UNUSED */
+	PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h
new file mode 100644
index 0000000000..a214a50eef
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0283,	// Codec Vendor / Device ID: Realtek ALC283
+	0x10ec0283,	// Subsystem ID
+	0x0000000e,	// Number of jacks (NID entries)
+
+	0x0017ff00,	// Function Reset
+	0x0017ff00,	// Double Function Reset
+	0x000F0000,	// Pad - get vendor id
+	0x000F0002,	// Pad - get revision id
+
+	/* Bits 31:28 - Codec Address */
+	/* Bits 27:20 - NID */
+	/* Bits 19:8 - Verb ID */
+	/* Bits 7:0  - Payload */
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x12) DMIC - Internal MIC */
+	// group 3, cap 0
+	// no connector, no jack detect
+	// mic in, digital
+	// fixed function, internal
+	AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
+
+	/* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */
+	// group 1, cap 0
+	// no connector, no jack detect
+	// speaker out, analog
+	// fixed function, internal, Location N/A
+	AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+	/* Pin Complex (NID 0x17) MONO Out - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+	/* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+	/* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */
+	// group2, cap 0
+	// black, jack detect
+	// Mic in, 3.5mm Jack
+	// connector, External left panel
+	AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020),
+
+	/* Pin Complex (NID 0x1A) LINE1 - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+	/* Pin Complex (NID 0x1B) LINE2 - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+	/* Pin Complex (NID 0x1D) PCBeep */
+	// eapd low on ex-amp, laptop, custom enable
+	// mute spkr on hpout
+	// pcbeep en able, checksum
+	// no physical, Internal, Location N/A
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
+
+	/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/
+	AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+	/* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/
+	// group2, cap 1
+	// black, jack detect
+	// HPOut, 3.5mm Jack
+	// connector, left panel
+	AZALIA_PIN_CFG(0x0, 0x21, 0x03211021),
+
+	/* Undocumented settings from Realtek (needed for beep_gen) */
+	/* Widget node 0x20 */
+	0x02050010,
+	0x02040c20,
+	0x0205001b,
+	0x0204081b,
+
+	/* Tuned jack detection */
+	0x02050043,
+	0x0204A614,
+	0x02050047,
+	0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+	0x00170500,	/* power up everything (codec, dac, adc, mixers)  */
+	0x01470740,	/* enable speaker out */
+	0x01470c02,	/* set speaker EAPD pin */
+	0x0143b01f,	/* unmute speaker */
+	0x00c37100,	/* unmute mixer nid 0xc input 1 */
+	0x00b37410,	/* unmute mixer nid 0xb beep input and set volume */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h
new file mode 100644
index 0000000000..0adc5890eb
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/onboard.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#define BOARD_TRACKPAD_NAME		"trackpad"
+#define BOARD_TRACKPAD_IRQ		37	/* PIRQV */
+#define BOARD_TRACKPAD_WAKE_GPIO	12	/* GPIO12 */
+#define BOARD_TRACKPAD_I2C_BUS		1	/* I2C0 */
+#define BOARD_TRACKPAD_I2C_ADDR		0x2C
+
+#define BOARD_TOUCHSCREEN_NAME		"touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ		38	/* PIRQW */
+#define BOARD_TOUCHSCREEN_WAKE_GPIO	25	/* GPIO25 */
+#define BOARD_TOUCHSCREEN_I2C_BUS	2	/* I2C1 */
+#define BOARD_TOUCHSCREEN_I2C_ADDR	0x10
+
+#define BOARD_WLAN_WAKE_GPIO		10	/* GPIO10 */
+#define BOARD_PP3300_CODEC_GPIO		45	/* GPIO45 */
+#define BOARD_WLAN_DISABLE_GPIO		46	/* GPIO46 */
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/spd.h b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h
new file mode 100644
index 0000000000..a7df6f425c
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/spd.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Sage Electronic Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN			256
+
+#define SPD_DRAM_TYPE		2
+#define SPD_DRAM_DDR3		0x0b
+#define SPD_DRAM_LPDDR3		0xf1
+#define SPD_DENSITY_BANKS	4
+#define SPD_ADDRESSING		5
+#define SPD_ORGANIZATION	7
+#define SPD_BUS_DEV_WIDTH	8
+#define SPD_PART_OFF		128
+#define SPD_PART_LEN		18
+
+/* Lulu board memory configuration GPIOs */
+#define SPD_GPIO_BIT0		13
+#define SPD_GPIO_BIT1		9
+#define SPD_GPIO_BIT2		47
+#define SPD_GPIO_BIT3		8
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h
new file mode 100644
index 0000000000..0b66c0b58f
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/include/variant/thermal.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID		0	/* PECI */
+#define CTL_TDP_POWER_LIMIT		12	/* 12W */
+#define CTL_TDP_THRESHILD_NORMAL	0	/*Normal TDP Threshold*/
+#define CTL_TDP_THRESHOLD_OFF		85	/* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON		90	/* Limited at 90C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE			105
+
+#endif
diff --git a/src/mainboard/google/auron/variants/lulu/pei_data.c b/src/mainboard/google/auron/variants/lulu/pei_data.c
new file mode 100644
index 0000000000..be7626c4d7
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/pei_data.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 1;
+
+	/* One installed DIMM per channel -- can be changed by SPD init */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	/* P0: Port B, CN01 (IOBoard) */
+	pei_data_usb2_port(pei_data, 0, 0x0150, 1, 0,
+			   USB_PORT_BACK_PANEL);
+	/* P1: Port A, CN01 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 2,
+			   USB_PORT_BACK_PANEL);
+	/* P2: CCD */
+	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P3: BT */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Empty */
+	pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P5: EMPTY */
+	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P6: SD Card */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_FLEX);
+	/* P7: EMPTY */
+	pei_data_usb2_port(pei_data, 7, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+
+	/* P0: PORTB*/
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P1: PORTA */
+	pei_data_usb3_port(pei_data, 1, 1, 2, 0);
+	/* P2: EMPTY */
+	pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+	/* P3: EMPTY */
+	pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}
diff --git a/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc
new file mode 100644
index 0000000000..bc1454f202
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/Makefile.inc
@@ -0,0 +1,51 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Sage Electronic Engineering
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13, GPIO8}
+SPD_SOURCES  = micron_2GiB_dimm_MT41K256M16HA-125	# 0b0000 2GB
+SPD_SOURCES += empty					# 0b0001
+SPD_SOURCES += empty					# 0b0010
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0	# 0b0011 2GB
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0	# 0b0100 2GB
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0	# 0b0101 4GB
+SPD_SOURCES += empty					# 0b0110
+SPD_SOURCES += empty					# 0b0111
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125	# 0b1000 4GB
+SPD_SOURCES += micron_4GiB_dimm_MT41K512M16TNA-125	# 0b1001 8GB
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA		# 0b1010 2GB
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA		# 0b1011 4GB
+SPD_SOURCES += hynix_4GiB_dimm_H5TC8G63CMR-PBA		# 0b1100 8GB
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0	# 0b1101 4GB
+SPD_SOURCES += samsung_4GiB_dimm_K4B8G1646Q-MYK0	# 0b1110 8GB
+SPD_SOURCES += empty					# 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
new file mode 100644
index 0000000000..e83f7e83f7
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000000..ebb10f353f
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
new file mode 100644
index 0000000000..3239846324
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
@@ -0,0 +1,33 @@
+# H5TC8G63CMR-PBA
+92 13 0b 03 04 19 02 0a
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 80 00 00 00 00 00 00
+00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 1f 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 b2 a3
+48 4d 54 38 35 31 53 36
+43 4d 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000000..91d816d4ea
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
new file mode 100644
index 0000000000..0a27768a36
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
@@ -0,0 +1,33 @@
+# MT41K512M16TNA-125:E
+92 11 0b 03 04 19 02 0A
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 05
+00 80 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 7f c1
+38 4b 54 53 35 31 32 36
+34 48 44 5a 2d 31 47 36
+45 31 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
new file mode 100644
index 0000000000..5937a888ea
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646E-BYK0
+92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F
+4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 0000000000..d6b0770334
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646Q-HYK0
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex b/src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
new file mode 100644
index 0000000000..4e7d8e41d8
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B8G1646Q-MYK0
+92 12 0B 03 04 19 02 0A 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 80 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 1F 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00
+4D 34 37 31 42 35 31 37 34 51 4D 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c
new file mode 100644
index 0000000000..ac99f5c7bc
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Sage Electronic Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <variant/gpio.h>
+#include <variant/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+	const int spd_banks[8] = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	const int spd_capmb[8] = {  1,  2,  4,  8, 16, 32, 64,  0 };
+	const int spd_rows[8]  = { 12, 13, 14, 15, 16, -1, -1, -1 };
+	const int spd_cols[8]  = {  9, 10, 11, 12, -1, -1, -1, -1 };
+	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
+	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
+	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	char spd_name[SPD_PART_LEN+1] = { 0 };
+
+	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+	int rows  = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+	int cols  = spd_cols[spd[SPD_ADDRESSING] & 7];
+	int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+	int devw  = spd_devw[spd[SPD_ORGANIZATION] & 7];
+	int busw  = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+	/* Module type */
+	printk(BIOS_INFO, "SPD: module type is ");
+	switch (spd[SPD_DRAM_TYPE]) {
+	case SPD_DRAM_DDR3:
+		printk(BIOS_INFO, "DDR3\n");
+		break;
+	case SPD_DRAM_LPDDR3:
+		printk(BIOS_INFO, "LPDDR3\n");
+		break;
+	default:
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		break;
+	}
+
+	/* Module Part Number */
+	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+	spd_name[SPD_PART_LEN] = 0;
+	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+	printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+	       , banks, ranks, rows, cols);
+	printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+	printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+	       devw, busw);
+
+	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+		printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+		       capmb / 8 * busw / devw * ranks);
+	}
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+	int spd_bits[4] = {
+		SPD_GPIO_BIT0,
+		SPD_GPIO_BIT1,
+		SPD_GPIO_BIT2,
+		SPD_GPIO_BIT3
+	};
+	int spd_gpio[4];
+	int spd_index;
+	size_t spd_file_len;
+	char *spd_file;
+
+	spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+	spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+	spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+	spd_gpio[3] = get_gpio(SPD_GPIO_BIT3);
+
+	spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
+		(spd_gpio[1] << 1) | spd_gpio[0];
+
+	printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+		spd_index,
+		spd_bits[3], spd_gpio[3],
+		spd_bits[2], spd_gpio[2],
+		spd_bits[1], spd_gpio[1],
+		spd_bits[0], spd_gpio[0]);
+
+	spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+		spd_index = 0;
+	}
+
+	if (spd_file_len < SPD_LEN)
+		die("Missing SPD data.");
+
+
+	/* CH0 */
+	memcpy(pei_data->spd_data[0][0],
+		spd_file + (spd_index * SPD_LEN), SPD_LEN);
+
+	/* CH1 not used in 2GB configurations */
+	if (!((spd_index == 0b0000) || (spd_index == 0b0011) ||
+	    (spd_index == 0b1010))) {
+		memcpy(pei_data->spd_data[1][0],
+			spd_file + (spd_index * SPD_LEN), SPD_LEN);
+	}
+
+	/* Make sure a valid SPD was found */
+	if (pei_data->spd_data[0][0][0] == 0)
+		die("Invalid SPD data.");
+
+	mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c
new file mode 100644
index 0000000000..084d4d1300
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/variant.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <soc/romstage.h>
+#include <variant/onboard.h>
+#include <mainboard/google/auron/variant.h>
+
+int variant_smbios_data(device_t dev, int *handle,
+				 unsigned long *current)
+{
+	int len = 0;
+
+	len += smbios_write_type41(
+		current, handle,
+		BOARD_TRACKPAD_NAME,		/* name */
+		BOARD_TRACKPAD_IRQ,		/* instance */
+		BOARD_TRACKPAD_I2C_BUS,		/* segment */
+		BOARD_TRACKPAD_I2C_ADDR,	/* bus */
+		0,				/* device */
+		0);				/* function */
+
+	len += smbios_write_type41(
+		current, handle,
+		BOARD_TOUCHSCREEN_NAME,		/* name */
+		BOARD_TOUCHSCREEN_IRQ,		/* instance */
+		BOARD_TOUCHSCREEN_I2C_BUS,	/* segment */
+		BOARD_TOUCHSCREEN_I2C_ADDR,	/* bus */
+		0,				/* device */
+		0);				/* function */
+
+	return len;
+}
+
+void variant_romstage_entry(struct romstage_params *rp)
+{
+	/* N/A for boards other than SAMUS */
+}
\ No newline at end of file