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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-08-01 13:53:04 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-03 08:07:31 +0000 |
| commit | 59962f3015055ccf746d286330a8ce4cc8edeccd (patch) | |
| tree | b64aa1790fb4df575f9e76985f2f96f7f1420b33 /src/mainboard/google/auron/variants/lulu | |
| parent | 4c1b6b31c0e608d3f4d01947814f4edc9b69bdea (diff) | |
| download | coreboot-59962f3015055ccf746d286330a8ce4cc8edeccd.tar.xz | |
mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver
These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.
Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.
Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/auron/variants/lulu')
| -rw-r--r-- | src/mainboard/google/auron/variants/lulu/devicetree.cb | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 84fc8c450c..622ea3488d 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -92,11 +92,7 @@ chip soc/intel/broadwell device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end |