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authorMatt DeVillier <matt.devillier@gmail.com>2018-08-01 13:53:04 -0500
committerPatrick Georgi <pgeorgi@google.com>2018-08-03 08:07:31 +0000
commit59962f3015055ccf746d286330a8ce4cc8edeccd (patch)
treeb64aa1790fb4df575f9e76985f2f96f7f1420b33 /src/mainboard/google/auron
parent4c1b6b31c0e608d3f4d01947814f4edc9b69bdea (diff)
downloadcoreboot-59962f3015055ccf746d286330a8ce4cc8edeccd.tar.xz
mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver
These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/auron')
-rw-r--r--src/mainboard/google/auron/variants/auron_paine/devicetree.cb6
-rw-r--r--src/mainboard/google/auron/variants/auron_yuna/devicetree.cb6
-rw-r--r--src/mainboard/google/auron/variants/gandof/devicetree.cb8
-rw-r--r--src/mainboard/google/auron/variants/lulu/devicetree.cb6
-rw-r--r--src/mainboard/google/auron/variants/samus/devicetree.cb6
5 files changed, 6 insertions, 26 deletions
diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
index 5872cf293c..b31d82979c 100644
--- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
@@ -91,11 +91,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
+ device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
index 34051a727f..3c00ec954f 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
@@ -91,11 +91,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
+ device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb
index 06ff8ae3b6..118e646ee0 100644
--- a/src/mainboard/google/auron/variants/gandof/devicetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb
@@ -90,12 +90,8 @@ chip soc/intel/broadwell
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
- chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb
index 84fc8c450c..622ea3488d 100644
--- a/src/mainboard/google/auron/variants/lulu/devicetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb
@@ -92,11 +92,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
+ device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb
index d12762d60c..a6c2feae56 100644
--- a/src/mainboard/google/auron/variants/samus/devicetree.cb
+++ b/src/mainboard/google/auron/variants/samus/devicetree.cb
@@ -95,11 +95,7 @@ chip soc/intel/broadwell
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
- # Rising edge interrupt
- register "irq_polarity" = "2"
- device pnp 0c31.0 on
- irq 0x70 = 10
- end
+ device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end