diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-23 23:41:53 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-27 03:03:16 +0200 |
| commit | 5029a1668e0ca99ac64210967e22c971b0395efa (patch) | |
| tree | f67df6c276760e91bdb49a4aab393b6894f81408 /src/mainboard/google/auron | |
| parent | 3795b03b69129367d57c93033785d7877aabc2cc (diff) | |
| download | coreboot-5029a1668e0ca99ac64210967e22c971b0395efa.tar.xz | |
ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeec
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/auron')
| -rw-r--r-- | src/mainboard/google/auron/acpi/ec.asl | 8 | ||||
| -rw-r--r-- | src/mainboard/google/auron/acpi/mainboard.asl | 14 |
2 files changed, 8 insertions, 14 deletions
diff --git a/src/mainboard/google/auron/acpi/ec.asl b/src/mainboard/google/auron/acpi/ec.asl index e25cd295a3..5740c27d32 100644 --- a/src/mainboard/google/auron/acpi/ec.asl +++ b/src/mainboard/google/auron/acpi/ec.asl @@ -19,5 +19,13 @@ /* variant configuration */ #include <variant/acpi/ec.asl> +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +/* + * There is no GPIO for LID, the EC pulses WAKE# pin instead. + * There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE. + */ +#define EC_ENABLE_WAKE_PIN 0x69 + /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index c5b9a83219..7910b6ee3f 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -18,20 +18,6 @@ Scope (\_SB) { - Device (LID0) - { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - - // There is no GPIO for LID, the EC pulses WAKE# pin instead. - // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE - Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP - } - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) |