diff options
author | Georg Wicherski <gwicherski@gmail.com> | 2015-10-15 12:58:04 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-03-10 16:54:39 +0100 |
commit | 422bf6b47226d68005003c17753fd30685e244c6 (patch) | |
tree | c83c1bc7696cdbe974857d5150085869c99d506e /src/mainboard/google/auron_paine/Kconfig | |
parent | 1eb1e3b8bf75984ad0d5b00fc34706f0e8391503 (diff) | |
download | coreboot-422bf6b47226d68005003c17753fd30685e244c6.tar.xz |
mainboards/google/auron_paine: add new port
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine
code originally from commit bd61dfd in Google branch
firmware-paine-6301.58.B .
Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: https://review.coreboot.org/11907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/auron_paine/Kconfig')
-rw-r--r-- | src/mainboard/google/auron_paine/Kconfig | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/mainboard/google/auron_paine/Kconfig b/src/mainboard/google/auron_paine/Kconfig new file mode 100644 index 0000000000..0b945eeee2 --- /dev/null +++ b/src/mainboard/google/auron_paine/Kconfig @@ -0,0 +1,65 @@ +if BOARD_GOOGLE_AURON_PAINE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_BROADWELL + select BOARD_ROMSIZE_KB_8192 + select EC_GOOGLE_CHROMEEC + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select INTEL_INT15 + +config CHROMEOS + select CHROMEOS_VBNV_CMOS + select LID_SWITCH + select CHROMEOS_RAMOOPS_DYNAMIC + select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +config MAINBOARD_DIR + string + default google/auron_paine + +config MAINBOARD_PART_NUMBER + string + default "Auron Paine" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + + +config MAINBOARD_FAMILY + string + depends on GENERATE_SMBIOS_TABLES + default "Google_Auron" +endif |