diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2016-12-18 11:59:58 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-12-22 18:37:56 +0100 |
commit | 45e11aa0a573aba1e4d8ae8dcd2cc87a8ca87dab (patch) | |
tree | 12f08b3aa147f80357afdd9ad437d8ac005caf05 /src/mainboard/google/auron_paine/acpi | |
parent | 0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d (diff) | |
download | coreboot-45e11aa0a573aba1e4d8ae8dcd2cc87a8ca87dab.tar.xz |
Add/Combine Broadwell Chromebooks using variant board scheme
Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/auron_paine/acpi')
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/ec.asl | 20 | ||||
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl | 82 | ||||
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/mainboard.asl | 118 | ||||
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/platform.asl | 82 | ||||
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/superio.asl | 25 | ||||
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/thermal.asl | 201 | ||||
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/video.asl | 38 |
7 files changed, 0 insertions, 566 deletions
diff --git a/src/mainboard/google/auron_paine/acpi/ec.asl b/src/mainboard/google/auron_paine/acpi/ec.asl deleted file mode 100644 index f7c8e273fb..0000000000 --- a/src/mainboard/google/auron_paine/acpi/ec.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/auron_paine/ec.h> - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl b/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9839..0000000000 --- a/src/mainboard/google/auron_paine/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/auron_paine/acpi/mainboard.asl b/src/mainboard/google/auron_paine/acpi/mainboard.asl deleted file mode 100644 index fe68e3015b..0000000000 --- a/src/mainboard/google/auron_paine/acpi/mainboard.asl +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/auron_paine/onboard.h> - -Scope (\_SB) -{ - Device (LID0) - { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - - - // There is no GPIO for LID, the EC pulses WAKE# pin instead. - // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE - Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP - } - - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } -} - -/* - * LPC Trusted Platform Module - */ -Scope (\_SB.PCI0.LPCB) - { - #include <drivers/pc80/tpm/acpi/tpm.asl> -} - -Scope (\_SB.PCI0.I2C0) -{ - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 1) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (Local0) - } - } - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.RP01) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - - /* GPIO10 is WLAN_WAKE_L_Q */ - Name (GPIO, 10) - - Name (_PRW, Package() { GPIO, 3 }) - - Method (_DSW, 3, NotSerialized) - { - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GPIO.GWAK (^GPIO) - } - } - } -} diff --git a/src/mainboard/google/auron_paine/acpi/platform.asl b/src/mainboard/google/auron_paine/acpi/platform.asl deleted file mode 100644 index 1bd054da06..0000000000 --- a/src/mainboard/google/auron_paine/acpi/platform.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) - Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) - } - - /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) - Notify (\_SB.LID0, 0x80) - } - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/auron_paine/acpi/superio.asl b/src/mainboard/google/auron_paine/acpi/superio.asl deleted file mode 100644 index 07d6b23e53..0000000000 --- a/src/mainboard/google/auron_paine/acpi/superio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/auron_paine/ec.h> - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/auron_paine/acpi/thermal.asl b/src/mainboard/google/auron_paine/acpi/thermal.asl deleted file mode 100644 index 2221abc3a7..0000000000 --- a/src/mainboard/google/auron_paine/acpi/thermal.asl +++ /dev/null @@ -1,201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/auron_paine/thermal.h> - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - Method (TCHK, 0, Serialized) - { - // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) - - // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { - Return (CTOK(0)) - } - - // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { - Return (CTOK(0)) - } - - // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { - Return (CTOK(0)) - } - - // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { - Return (CTOK(0)) - } - - // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) - - // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) - Return (Local0) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for EC to re-poll - Sleep (1000) - - // Re-read temperature from EC - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - - /* CTDP Down */ - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (CTL_TDP_THRESHOLD_OFF)) - } Else { - Return (CTOK (CTL_TDP_THRESHOLD_ON)) - } - } - - /* CTDP Nominal */ - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) - } Else { - Return (CTOK (CTL_TDP_THRESHILD_NORMAL)) - } - } - - Name (_AL0, Package () { TDP0 }) - Name (_AL1, Package () { TDP1 }) - - PowerResource (TNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (0, \FLVL) - - /* Enable Power Limit */ - \_SB.PCI0.MCHC.CTLE (CTL_TDP_POWER_LIMIT) - - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (1, \FLVL) - - /* Disable Power Limit */ - \_SB.PCI0.MCHC.CTLD () - - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (TNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - Device (TDP0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { TNP0 }) - } - - Device (TDP1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { TNP1 }) - } - } -} diff --git a/src/mainboard/google/auron_paine/acpi/video.asl b/src/mainboard/google/auron_paine/acpi/video.asl deleted file mode 100644 index 68946552a6..0000000000 --- a/src/mainboard/google/auron_paine/acpi/video.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} |