diff options
| author | Georg Wicherski <gwicherski@gmail.com> | 2015-10-15 12:58:04 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-10 16:54:39 +0100 |
| commit | 422bf6b47226d68005003c17753fd30685e244c6 (patch) | |
| tree | c83c1bc7696cdbe974857d5150085869c99d506e /src/mainboard/google/auron_paine/chromeos.fmd | |
| parent | 1eb1e3b8bf75984ad0d5b00fc34706f0e8391503 (diff) | |
| download | coreboot-422bf6b47226d68005003c17753fd30685e244c6.tar.xz | |
mainboards/google/auron_paine: add new port
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine
code originally from commit bd61dfd in Google branch
firmware-paine-6301.58.B .
Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: https://review.coreboot.org/11907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/auron_paine/chromeos.fmd')
| -rw-r--r-- | src/mainboard/google/auron_paine/chromeos.fmd | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/auron_paine/chromeos.fmd b/src/mainboard/google/auron_paine/chromeos.fmd new file mode 100644 index 0000000000..21b39c0e21 --- /dev/null +++ b/src/mainboard/google/auron_paine/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + RW_SECTION_A@0x0 0xf0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0xdffc0 + RW_FWID_A@0xeffc0 0x40 + } + RW_SECTION_B@0xf0000 0xf0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0xdffc0 + RW_FWID_B@0xeffc0 0x40 + } + RW_MRC_CACHE@0x1e0000 0x10000 + RW_ELOG@0x1f0000 0x4000 + RW_SHARED@0x1f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1f8000 0x2000 + RW_UNUSED@0x1fa000 0x6000 + RW_LEGACY@0x200000 0x200000 + WP_RO@0x400000 0x200000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x1f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x100000 + } + } + } +} |