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authorGeorg Wicherski <gwicherski@gmail.com>2015-10-15 12:58:04 +0200
committerMartin Roth <martinroth@google.com>2016-03-10 16:54:39 +0100
commit422bf6b47226d68005003c17753fd30685e244c6 (patch)
treec83c1bc7696cdbe974857d5150085869c99d506e /src/mainboard/google/auron_paine/romstage.c
parent1eb1e3b8bf75984ad0d5b00fc34706f0e8391503 (diff)
downloadcoreboot-422bf6b47226d68005003c17753fd30685e244c6.tar.xz
mainboards/google/auron_paine: add new port
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine code originally from commit bd61dfd in Google branch firmware-paine-6301.58.B . Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: https://review.coreboot.org/11907 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/auron_paine/romstage.c')
-rw-r--r--src/mainboard/google/auron_paine/romstage.c48
1 files changed, 48 insertions, 0 deletions
diff --git a/src/mainboard/google/auron_paine/romstage.c b/src/mainboard/google/auron_paine/romstage.c
new file mode 100644
index 0000000000..ce4af5e442
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+++ b/src/mainboard/google/auron_paine/romstage.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
+#include <mainboard/google/auron_paine/spd/spd.h>
+#include "gpio.h"
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ struct pei_data pei_data;
+
+ post_code(0x32);
+
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
+
+ /* Initialize GPIOs */
+ init_gpios(mainboard_gpio_config);
+
+ /* Fill out PEI DATA */
+ memset(&pei_data, 0, sizeof(pei_data));
+ mainboard_fill_pei_data(&pei_data);
+ mainboard_fill_spd_data(&pei_data);
+ rp->pei_data = &pei_data;
+
+ /* Call into the real romstage main with this board's attributes. */
+ romstage_common(rp);
+}