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| author | FrankChu <frank_chu@pegatron.corp-partner.google.com> | 2021-03-23 18:24:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-25 07:50:17 +0000 |
| commit | 6902263dca82c9e08d48554cc1daffc8dfd6b6de (patch) | |
| tree | 8e4f88c9a3d22103368a17417b5b19c776458aea /src/mainboard/google/beltino/romstage.c | |
| parent | 2bb7896c366258c46e8125aad63ffe09c87ad5ec (diff) | |
| download | coreboot-6902263dca82c9e08d48554cc1daffc8dfd6b6de.tar.xz | |
mb/google/volteer: Collis: Update SPD table
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:182227204
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/beltino/romstage.c')
0 files changed, 0 insertions, 0 deletions