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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 14:03:40 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-28 08:52:37 +0000 |
| commit | 9f78127b61632cbb138bdbfa650c2e9965440d3b (patch) | |
| tree | b0f146a3725bcd86b83242b9abb465bd27829681 /src/mainboard/google/beltino | |
| parent | 172bcc835f0d214444398c57a0ca9eddd2941ecf (diff) | |
| download | coreboot-9f78127b61632cbb138bdbfa650c2e9965440d3b.tar.xz | |
lynxpoint: Factor out PIRQ routing from devicetree
All boards disable PIRQs. They aren't used on modern OSes anyway.
Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/beltino')
| -rw-r--r-- | src/mainboard/google/beltino/devicetree.cb | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 171b93f81d..8fdfbd79a0 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -36,15 +36,6 @@ chip northbridge/intel/haswell device pci 03.0 on end # mini-hd audio chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x80" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x80" - register "pirqd_routing" = "0x80" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" |