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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 23:52:34 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-12 10:10:11 +0000
commitd37b7d89fd362242fd5da11303c7bb18bf78afcf (patch)
tree12b4b962e423fb10816b848cb5a5143fd79fc84e /src/mainboard/google/beltino
parent3ac92b7c93addd8e75096162f88e65a3a54fcab0 (diff)
downloadcoreboot-d37b7d89fd362242fd5da11303c7bb18bf78afcf.tar.xz
haswell: Add function to retrieve SPD addresses
And use it instead of directly writing to the MRC struct. Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/google/beltino')
-rw-r--r--src/mainboard/google/beltino/romstage.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 839cd6c743..8410d04923 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -39,10 +40,14 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[2] = 0xa4;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
pei_data->dq_pins_interleaved = 1;
pei_data->usb_xhci_on_resume = 1;