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authorAngel Pons <th3fanbus@gmail.com>2020-07-04 01:24:59 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-12 11:16:12 +0000
commit8aab7876d186ed9a8e978ec06a83a46f74a6179b (patch)
tree5069b7aa81401f9606021cc8e25f9d52192f7ea7 /src/mainboard/google/beltino
parent39a6093d7937dec85077f754fbcaa2e2be493eae (diff)
downloadcoreboot-8aab7876d186ed9a8e978ec06a83a46f74a6179b.tar.xz
haswell: Move some MRC settings to devicetree
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/beltino')
-rw-r--r--src/mainboard/google/beltino/devicetree.cb4
-rw-r--r--src/mainboard/google/beltino/romstage.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index f4c9e850ab..304f3cf38f 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -9,6 +9,10 @@ chip northbridge/intel/haswell
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
+ register "dq_pins_interleaved" = "true"
+
+ register "usb_xhci_on_resume" = "true"
+
device cpu_cluster 0 on
chip cpu/intel/haswell
device lapic 0 on end
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 8410d04923..ee146301ec 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -48,10 +48,6 @@ void mb_get_spd_map(uint8_t spd_map[4])
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->ec_present = 0;
- pei_data->dq_pins_interleaved = 1;
- pei_data->usb_xhci_on_resume = 1;
-
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */