diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 18:34:22 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 10:00:49 +0000 |
| commit | 411ae05f1daf2cc877eab76a7f961f735da2c861 (patch) | |
| tree | 5a5474a2bef995af174c7de0f8ba58a2cd055f4e /src/mainboard/google/beltino | |
| parent | 3e72f87fe72434216fef63bdcb07ecd63ca03ac6 (diff) | |
| download | coreboot-411ae05f1daf2cc877eab76a7f961f735da2c861.tar.xz | |
mb/google/beltino: Factor out common MRC settings
There's no need to redefine common settings.
Change-Id: I62f5014cf1fea093aee17023b48fd4d404279410
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/google/beltino')
| -rw-r--r-- | src/mainboard/google/beltino/romstage.c | 100 |
1 files changed, 46 insertions, 54 deletions
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 54960928d0..015b64313f 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -44,60 +44,52 @@ void mainboard_config_rcba(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data mainboard_pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, - .ec_present = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - // Enable 2x refresh mode - .ddr_refresh_2x = 1, - .dq_pins_interleaved = 1, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = 1, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0064, 1, 0, /* P0: VP8 */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 0, /* P1: Port A, CN22 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 1, /* P2: Port B, CN23 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P4: Port C, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, 2, /* P5: Port D, CN25 */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ - USB_PORT_INTERNAL }, - { 0x0000, 0, 0, /* P7: N/C */ - USB_PORT_SKIP }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; CN22 */ - { 1, 1 }, /* P2; CN23 */ - { 1, 2 }, /* P3; CN25 */ - { 1, 2 }, /* P4; CN25 */ - }, + pei_data->system_type = 5; /* ULT */ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[2] = 0xa4; + pei_data->ec_present = 0; + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + /* Enable 2x refresh mode */ + pei_data->ddr_refresh_2x = 1; + pei_data->dq_pins_interleaved = 1; + pei_data->max_ddr3_freq = 1600; + pei_data->usb_xhci_on_resume = 1; + + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0064, 1, 0, /* P0: VP8 */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN22 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 1, /* P2: Port B, CN23 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P4: Port C, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, 2, /* P5: Port D, CN25 */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ + USB_PORT_INTERNAL }, + { 0x0000, 0, 0, /* P7: N/C */ + USB_PORT_SKIP }, + }; + + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; CN22 */ + { 1, 1 }, /* P2; CN23 */ + { 1, 2 }, /* P3; CN25 */ + { 1, 2 }, /* P4; CN25 */ }; - *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); } |