diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-06-24 14:57:40 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-12-12 22:12:09 +0100 |
| commit | 3ece50d9db35eecef557fc6ad8cc404224cfc9ac (patch) | |
| tree | 704280460756465755f37a12830167e38865843d /src/mainboard/google/bolt/Kconfig | |
| parent | 0a7c49efa02b770f9f4f723633f82784be7ae6b8 (diff) | |
| download | coreboot-3ece50d9db35eecef557fc6ad8cc404224cfc9ac.tar.xz | |
bolt: Initial mainboard commit
BUG=chrome-os-partner:20448
BRANCH=none
TEST=emerge-bolt chromeos-coreboot-bolt
Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59843
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4330
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/bolt/Kconfig')
| -rw-r--r-- | src/mainboard/google/bolt/Kconfig | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig new file mode 100644 index 0000000000..1d2b2594d2 --- /dev/null +++ b/src/mainboard/google/bolt/Kconfig @@ -0,0 +1,53 @@ +if BOARD_GOOGLE_BOLT + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_LYNXPOINT_LP + select BOARD_ROMSIZE_KB_8192 + select EC_GOOGLE_CHROMEEC + select EC_SOFTWARE_SYNC + select VIRTUAL_DEV_SWITCH + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_CHROMEOS + select EXTERNAL_MRC_BLOB + select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB + select MONOTONIC_TIMER_MSR + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config MAINBOARD_DIR + string + default google/bolt + +config MAINBOARD_PART_NUMBER + string + default "Bolt" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif |