summaryrefslogtreecommitdiff
path: root/src/mainboard/google/bolt/acpi/mainboard.asl
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2013-06-24 14:57:40 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-12-12 22:12:09 +0100
commit3ece50d9db35eecef557fc6ad8cc404224cfc9ac (patch)
tree704280460756465755f37a12830167e38865843d /src/mainboard/google/bolt/acpi/mainboard.asl
parent0a7c49efa02b770f9f4f723633f82784be7ae6b8 (diff)
downloadcoreboot-3ece50d9db35eecef557fc6ad8cc404224cfc9ac.tar.xz
bolt: Initial mainboard commit
BUG=chrome-os-partner:20448 BRANCH=none TEST=emerge-bolt chromeos-coreboot-bolt Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59843 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4330 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/bolt/acpi/mainboard.asl')
-rw-r--r--src/mainboard/google/bolt/acpi/mainboard.asl110
1 files changed, 110 insertions, 0 deletions
diff --git a/src/mainboard/google/bolt/acpi/mainboard.asl b/src/mainboard/google/bolt/acpi/mainboard.asl
new file mode 100644
index 0000000000..c579499256
--- /dev/null
+++ b/src/mainboard/google/bolt/acpi/mainboard.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <mainboard/google/bolt/onboard.h>
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name(_HID, EisaId("PNP0C0D"))
+ Method(_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+ }
+
+ Device (TPAD)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 1)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name (_HID, EisaId("PNP0C0E"))
+
+ Name (_CRS, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+
+ VendorShort (ADDR)
+ {
+ BOARD_TRACKPAD_I2C_ADDR
+ }
+ })
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
+
+ Device (TSCR)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 2)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name (_HID, EisaId("PNP0C0E"))
+
+ Name (_CRS, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+
+ VendorShort (ADDR)
+ {
+ BOARD_TOUCHSCREEN_I2C_ADDR
+ }
+ })
+
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+ Method (_DSW, 3, NotSerialized)
+ {
+ Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
+
+ If (LEqual (Arg0, 1)) {
+ // Enable GPIO as wake source
+ \_SB.PCI0.LPCB.GWAK (Local0)
+ }
+ }
+ }
+}