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authorAaron Durbin <adurbin@chromium.org>2016-07-26 11:48:06 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-27 21:25:06 +0200
commit139314bffd5ff29847661c536130d8d8d3e261bf (patch)
tree964701ca27fcf8ad741641b984c797986d60d261 /src/mainboard/google/bolt/acpi/superio.asl
parent60cc75df83f2da64132b6da6dd431417da6b2f4e (diff)
downloadcoreboot-139314bffd5ff29847661c536130d8d8d3e261bf.tar.xz
mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never made it out in the wild. Moreover, I don't think any of these boards exist any longer. Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15901 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/bolt/acpi/superio.asl')
-rw-r--r--src/mainboard/google/bolt/acpi/superio.asl25
1 files changed, 0 insertions, 25 deletions
diff --git a/src/mainboard/google/bolt/acpi/superio.asl b/src/mainboard/google/bolt/acpi/superio.asl
deleted file mode 100644
index b5d7c6eeeb..0000000000
--- a/src/mainboard/google/bolt/acpi/superio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-#include <mainboard/google/bolt/ec.h>
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>